intel electrical question

[jessem]

I understand basic electrical theory. DDR (Double Data Read) is as I understand it transmitting data on both halves of a sine wave. One clock cycle is one sine wave with a positive half upward and a negative half downward. What I do not understand is how Intel gets 4 transmissions of data, ie, 800 mhz out of one clock cycle. Is this all a marketing ploy or am I missing something in very basic electrical theory????

[Onlyonerhino]

Sounds like you understand DDR just fine. The reason that mobo manufacturers adverstise 800Mhz is because of a dual channel set up. Basically, with a dual channel Mobo and 2 identical sticks of DDR (stuck in the correct banks) each is accessed on a different bus, rather than one memory bus accessing both sticks. Thus, 800 Mhz. So bascially you get a transmission on the leading and trailing end of a cycle on a 200FSB = 400 Fsb x two channels = 800Fsb. I think it is somewhat of a hpye. Dual channel makes a diff on Intel, but very little of AMD IMO. In either case, it is definitely a let down from what I perceived dual channel with 800Mhz to be in terms of performance.

[john99]

Dual channel on a P4 make alot of differences, it quite noticeable.

[adslegend]

Doesn't Intel just have 2 signals per rise/fall of each clock cycle?

[adslegend]

Originally posted by Onlyonerhino
Sounds like you understand DDR just fine. The reason that mobo manufacturers adverstise 800Mhz is because of a dual channel set up. Basically, with a dual channel Mobo and 2 identical sticks of DDR (stuck in the correct banks) each is accessed on a different bus, rather than one memory bus accessing both sticks. Thus, 800 Mhz. So bascially you get a transmission on the leading and trailing end of a cycle on a 200FSB = 400 Fsb x two channels = 800Fsb. I think it is somewhat of a hpye. Dual channel makes a diff on Intel, but very little of AMD IMO. In either case, it is definitely a let down from what I perceived dual channel with 800Mhz to be in terms of performance.

I don't think you quite understood what he was asking. You say '200 FSB = 400 FSB x two channels = 800 Fsb'.

What you are saying is like dual channel for Athlon XP. The latency of half a CPU cycle is where the bottleneck lies. Just giving another memory channel will not help.

However, with the P4 a signal latency of a quarter of one CPU cycle means that the speed of the memory bus becomes the limiting factor, which is why running dual channel DDR is important on P4s.

[Onlyonerhino]

Originally posted by adslegend
I don't think you quite understood what he was asking. You say '200 FSB = 400 FSB x two channels = 800 Fsb'.

What you are saying is like dual channel for Athlon XP. The latency of half a CPU cycle is where the bottleneck lies. Just giving another memory channel will not help.

However, with the P4 a signal latency of a quarter of one CPU cycle means that the speed of the memory bus becomes the limiting factor, which is why running dual channel DDR is important on P4s.

You are correct and I misspoke. Intel uses quad pumping while AMDs transmitt data the rising and falling edge of the clock cycle, then taking this times two, because there are two memory channels theoretically would egual an effective 800fsb, execept the Athlon processor itself is the bottle neck.
And so yes, Dual channel makes a noticable difference on P4's but not on AMD's. I still don't think the differences IMO, even on the P4, is what you would expect by doubling the bandwidth.

[john99]

The P4 is actually being castrated when running in single channel.
We'er talking about an increase in memory bandwidth from 3.2g/s to 6.4g/s, that quite significant. Further more, the P4c, & e actually have a fsb bandwidth of 6.4g/s, so it would make full use of the dual channel bandwidth, which it can't do if it running in single channel. Hence the increase in performance is quite noticeable. It can save you a few hours of waiting if you'er doing video conversion.


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