Fsb

[Drchud]

I am running on an Athlon XP 2100+ and a MSI KT3 Ultra motherboard - PC2100 DDR ram.

My bios says the FSB is set to 133mhz. Both my processor and motherboard are 266mhz FSB compatible. Is the 266 derived from 133mhz x 2 somewhere - or is my systems fsb currently running at 133mhz and not to its full potential?

[alcan60283]

Yes. Your components are running at 266mhz. 133mhz X 2 effective DDR speed. Double Data Rate = FSB X 2

[Drchud]

Heh ok I figured that is how things worked - thank you for the clarification

[alcan60283]

No problem. Any time. That's what I'm here for.

[as good as it gets]

yah to clarify DDR is double data rate ie 2x the data rate, are you aware of how this is done?

normal SDRam is one lot of data per clock cycle, think of it as a human with one bucket ie per trip only one load

ddr however uses both arms thus 2 x the data per trip

so yes every thing is x 2 hence 133 ddr is equal to 266 x 1

also p4 now has Quad pumped fsb

this means now there are 2 people with 2 buckets each but one waits a little bit for the first to go, ( the are out of phase by 90 degrees)

[Tekime]

Originally posted by as good as it gets

...
also p4 now has Quad pumped fsb


As I understand DDR takes advantage of the rising and falling edges of the cycle to send data; do you know how a 4xFSB would compare to this? Probably two instructions per edge?

[as good as it gets]

from what i understand it is 2 ddr clock cycles out of phase by 90 degreees ie a sin and cosin graph.

[Un4given]

Originally posted by as good as it gets
from what i understand it is 2 ddr clock cycles out of phase by 90 degreees ie a sin and cosin graph.

That is correct.

[Tekime]

Originally posted by as good as it gets
from what i understand it is 2 ddr clock cycles out of phase by 90 degreees ie a sin and cosin graph.

Couldn't we take advantage of more wave phases than 2? Could we theoretically build a memory technology that has 10, 50 or even 1000 ddr clock cycles all out of phase? Of course, the memory and memory controller would have to be able to handle this, but what's stopping us?

[Un4given]

Originally posted by Tekime


Couldn't we take advantage of more wave phases than 2? Could we theoretically build a memory technology that has 10, 50 or even 1000 ddr clock cycles all out of phase? Of course, the memory and memory controller would have to be able to handle this, but what's stopping us?

That would be impractical in terms of implementation.

[Tekime]

I kind of figured, since they aren't doing it, but do you know why?

I can understand 100 or 1000 being very unrealistic, but do you think this may be a technique involved in advancing memory technology some more, or is two phases just the limit before the practicality isn't worth the advantage?

Just curious, it seems like a very interesting concept

[muisejt]

Originally posted by Tekime


Couldn't we take advantage of more wave phases than 2? Could we theoretically build a memory technology that has 10, 50 or even 1000 ddr clock cycles all out of phase? Of course, the memory and memory controller would have to be able to handle this, but what's stopping us?

There is a clock signal that keeps everything in sync and it is a square wave

With DDR memory the data is sent twice a cycle, at the rise and fall of the wave because the electronics are edge triggered (sense the change in voltage)

Basically as memory chips get faster the operation frequencys go up giving you faster RAM (PC-66, PC-100, PC-133, 133-DDR (266MHz) and now the jump to DDR to 166-DDR (333MHz)