I don't understand how AMD's FSB works. How can the FSB run at 200Mhz when one has 100Mhz RAM in the comp. Explain.
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I don't understand how AMD's FSB works. How can the FSB run at 200Mhz when one has 100Mhz RAM in the comp. Explain.
AMD's front side bus actually uses a 100MHz base clock that is able to read two pieces of data per tick. Since this effectively doubles the bandwidth, people consider the front side bus 200MHz. Another example of this is the upcoming Pentium 4. The Pentium 4 also has a 100MHz base clock, but it can read 4 pieces of data per tick, so people say it has an effective 400MHz clock.Quote:
Originally posted by smtkr:
I don't understand how AMD's FSB works. How can the FSB run at 200Mhz when one has 100Mhz RAM in the comp. Explain.
It's up to the chipset on the motherboard to make the translations between different clock speeds. You will notice chipsets such as VIA's KT133 actually translates the 100MHz base clock of the Athlon to a 133MHz memory clock, which it can do through dividers.
The chipset for the Athlon is asynchronous. It has no fixed relationship between the memory bus and the processor FSB. As a result, when the chipset receives data from the processor it must hold it until the next clock cycle of the memory bus before sending it on. The same is true when data goes from memory to the processor.Quote:
Originally posted by smtkr:
I don't understand how AMD's FSB works. How can the FSB run at 200Mhz when one has 100Mhz RAM in the comp. Explain.
This introduces some latency and explains why a synchronous chipset like the BX can outperform an asynchronous one like the 820 or 815. (I have been told that the 815 can operate synchronously when the FSB and memory speed match but I have never confirmed this)
I expect that the chipset also has some form of buffer that allows it to store several transfers and send them to the memory/processor at the best time. (Reads are more important then writes)
A buffer like this would likely be required in any case since modern processors like the Athlon and PIII support having multiple outstanding memory operations.
So, basically, you can put 100mhz in with the PIV system and it will work just as well as it would with RDRAM? Because you are are saying that it would be effectively quadrupaling the speed of common 100mhz ram. It is essentially a "virtual" bus speed? Does this mean that it works similar to DDR RAM?
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I'm consistantly inconsistant!
Yes, it works similar to DDR RAM, DDR simply stands for double data rate. As already explained, two pieces of information are passed during one clock cycle.
By saying 100Mhz, I assume you're saying 100Mhz RAM, in which case, in theory, yes. If there was supoort in the chipset for non-RDRAM, you could just stick in PC100 or PC133 RAM.Quote:
So, basically, you can put 100mhz in with the PIV system and it will work just as well as it would with RDRAM?
You seem to be confused, smtkr. In a Pentium 4 system, you can only use Rambus memory. This is because of the logic that is present in the Memory Controller Hub (MCH) portion of the chipset. The MCH is designed to accept Rambus signals (which include information besides data), and translates them into front side bus protocol in order to communicate with the CPU. The MCH for the i850 chipset, which goes along with Pentium 4, is ONLY designed to do this for Rambus, not PC100. (Stop me if I'm going to fast https://www.sharkyforums.com/images/.../2005/06/5.gif ).Quote:
Originally posted by smtkr:
So, basically, you can put 100mhz in with the PIV system and it will work just as well as it would with RDRAM? Because you are are saying that it would be effectively quadrupaling the speed of common 100mhz ram. It is essentially a "virtual" bus speed? Does this mean that it works similar to DDR RAM?
Rambus is double data rate memory since two pieces of information are passed during one clock cycle (as LiquidGoop explains), so you can say it is ddr. However, you can't say it is DDR, because that is the name for SDRAM that operates at double data rate. Confused? Well, this is just brand labeling... nothing technical about it https://www.sharkyforums.com/images/.../2005/06/5.gif.
Also, you ask, "Because you are are saying that it would be effectively quadrupaling the speed of common 100mhz ram. It is essentially a "virtual" bus speed?"
I didn't say such a thing, and if anyone else is telling you this, they are mistaken. The front side bus of the Pentium 4 is effectively quadrupled by the logic in the MCH, and this logic has absolutely nothing to do with the memory portion of that chip. I also wouldn't call it a "virtual" bus speed, because data IS actually being received at 400MHz on the Pentium 4 front side bus. Transactions, on the other hand, travel at 100MHz. However, it gets complicated here because data is actaully PART of a transaction, and it happens to be the largest part. So, overall, I would say that effectively the Pentium 4 bus is 400MHz, because data, which is the largest piece of traffic, is transferred at 400MHz.
Hope this helps, and hopefully I didn't confuse you more. If you have any more questions, feel free to ask.
Moridin, I believe you are misusing the terms "synchronous" and "asynchronous". Synchronous means that data is latched on a clock, while Asynchronous means there is no clock present.Quote:
Originally posted by Moridin:
The chipset for the Athlon is asynchronous. It has no fixed relationship between the memory bus and the processor FSB. As a result, when the chipset receives data from the processor it must hold it until the next clock cycle of the memory bus before sending it on. The same is true when data goes from memory to the processor.
This introduces some latency and explains why a synchronous chipset like the BX can outperform an asynchronous one like the 820 or 815. (I have been told that the 815 can operate synchronously when the FSB and memory speed match but I have never confirmed this)
I expect that the chipset also has some form of buffer that allows it to store several transfers and send them to the memory/processor at the best time. (Reads are more important then writes)
A buffer like this would likely be required in any case since modern processors like the Athlon and PIII support having multiple outstanding memory operations.
If a motherboard were asynchronous, it would ask for data from memory, and then wait patiently for the data to return. The old Fast Page Memory (FPM) and Extended Data Output (EDO) memory that people used to use were asynchronous. Today's SDRAM, and even Rambus, are synchronous memory technologies.
In some motherboards, you will see something like 200MHz on the front side bus, and 133MHz on the memory bus. Such is the case in VIA's KT133 chipset. This is not done asynchronously, though. In fact, the same clock goes to both the memory AND front side bus. The difference is that they go through custom multipliers, which give the final speed of the clock. These multiplier cause an original clock to change frequency.
For example, in a motherboard that I know, the original clock comes from an 8MHz crystal, and it gets multiplied 4 times to achieve a 33MHz clock. Then that clock can be multiplied by 6 to achieve 200MHz for the front side bus, and by 4 to achieve 133MHz for memory.
The reason for this is that you can't generate a high frequency clock right off the bat, But you can generate a low frequency clock, and put it through very accurate clock multipliers. Hope this clears some stuff up for you.
So, pretty much, we'll be paying $2,000,000 for a PIV when they come out.
https://www.sharkyforums.com/images/.../2005/06/6.gif
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I'm consistantly inconsistant!
I was referring to the chipset, not the motherboard.Quote:
Originally posted by Arcadian:
Moridin, I believe you are misusing the terms "synchronous" and "asynchronous". Synchronous means that data is latched on a clock, while Asynchronous means there is no clock present.
In the context of the chipset I think this is exactly what is happening. An asynchronous chipset has no clock signal that fixes a relationship between the memory bus and the FSB so the two operate independently. A synchronous chipset on the other hand does have a clock signal that fixes a relationship between the FSB and the memory bus.
Wouldn't this "double dipping" of the ram all depend on the mother board's chipset and not the processor?
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I'm consistantly inconsistant!