Power Consumption Considerations of next generation CPU's

I just got out of a talk from Trevor Mudge, a Professor of Electrical and Computer Engineering at the University of Michigan.

The purpose of his talk was on Power Consumption of computers, for both the desktop computer and mobile computer devices such as PDA's and handhelds.

He has an interesting prospective on things. Though I am not sure I agree with him totally. He started by showing the trends in the Compaq Alpha chip and its huge power usage increase over the years (with minimal die size increase). He also talked about the recent versions of the AMD Athlon chip, but mainly focused on the Pentium 4. Basically he thinks that these microprocessors are going in the wrong direction. He believes that any kind of predictions microprocessors make are a waste of time and energy because they could be doing unneccesary calculations.

He talked further about the XScale technology (for those of you not aware, XScale is the StrongARM SA2 processor, Intel wants to stray away from calling it an ARM processor so they made a nifty new name) and how it has the ability to scale down its clock speed and power usage.

Basically, what it comes down to is he says the only way to reduce power consumption to a good level is parrellel processing. According to his talk, most of the modern microprocessors die (almost 40% in some cases) goes to the cache. He thinks that by doing muliple CPUs on a die that run at lower clock speeds you could get more performance from a system that uses less power (he used a bunch of forumlas to come to the conclusion that cutting clock frequency by 1/2 cuts power consumption by 1/4, thus two 500Mhz. CPUs would use 1/2 the power of one 1Ghz. CPU).

Basically this all seams to say that CMT (I think I am using the correct term here) is the way of the future, what do you guys think?

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Q: How many UGA students does it take to change a lightbulb?

A: Two, one to call a friend at GT and another to follow the directions.

Prediction increases performance by up to 30%. The question is does it increase power consumption by a similar amount. I would tend to think not, but even if it does the extra performance is likely critical to desktop and workstation applications. Servers on the other hand could indeed compensate by increasing parallelism.

SMT is a better solution then CMP IMO. SMT requires additional overhead, including a full OoO implementation. Beyond that however, SMT only requires an additional 5-10% more transistors. The advantage is that you can make very efficient use of your execution resources. In modern X86 processors your execution resources have less then 50% utilization, so you could double you performance on threaded apps for a very small price in power and transistors.

If you have enough thread level parallelism to keep all your execution resources busy power consumption and performance should go up by equal amounts when processor speed goes up. (The generally accepted formula is that P goes up with frequency and the square of the voltage) The benefit here is that single threaded applications are not artificially crippled.

Can you give us any information on why he suggests power consumption goes up as the square of the frequency? Was he just projecting power usage of actual processors? If that is what he was doing then you need to remember that a lot of additional circuitry (and therefor power) went into keeping IPC high.


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Life is complex. It has real and imaginary parts.

Though I can't remember all the parameters of the equation the main parts were Power = V^2*f+Vleak. There were more parameters to the V^2*f portion of the equation but I can't remember them off the top of my head.

They were basically all derived from Ohms law if I recall correctly. He was trying to fit a big speach into a little time slot so he was vague at best on some of the details.

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Q: How many UGA students does it take to change a lightbulb?

A: Two, one to call a friend at GT and another to follow the directions.

Quote:

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Originally posted by jtshaw:
Though I can't remember all the parameters of the equation the main parts were Power = V^2*f+Vleak. There were more parameters to the V^2*f portion of the equation but I can't remember them off the top of my head.

They were basically all derived from Ohms law if I recall correctly. He was trying to fit a big speach into a little time slot so he was vague at best on some of the details.

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So normally power is P=C*(V^2)*f, where f is frequency, V is voltage, C is capacitance. Note that it is Voltage squared and linear in frequency, which is why Moridin and I are confused.

Ya, I actually got a copy of his slides. He used Power=C*V^2*f+Vleak and then states in another slide that when you take 1/2 the frequency you get 1/4 the Power.. Which as you both pointed out doesn't make a damn bit of sense. I wonder if there is something he skipped because he was trying to cut the talk short, or maybe I just missed it because the semester is dwinding down and I haven't slept in 3 days:P He never even touched on exactly where they get the Vleak from, if it truely is just a Voltage it doesn't make sense either so maybe it has something to do with the clock frequency also. I wish I had a chance to sit down and actually talk to him one on one and ask him some questions, maybe I will try and do that tomorrow.

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Q: How many UGA students does it take to change a lightbulb?

A: Two, one to call a friend at GT and another to follow the directions.

Vleak is becoming a bigger problem as die size continues to shrink. It can amount to a rather large percentage of overall power usage. I would also think that this would be an argument for SMT and against CMP. SMT wouldn't add much in the way of leakage current, but CMP would since it adds additional execution resources in addition to control logic.