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Alright, I'm a little confused. How exactly would it be possible for the i850 to get a full 3.2 GB/s bandwidth from only one RIMM and a C/RIMM (kinda a space holder)?
See this thread for further info :
http://www.sharkyforums.com/ubb/Foru.../015277-2.html
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Duke of the OC Crusaders
System Specifications.
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Quote:
Originally posted by Mandorallen of Molynnr:
Alright, I'm a little confused. How exactly would it be possible for the i850 to get a full 3.2 GB/s bandwidth from only one RIMM and a C/RIMM (kinda a space holder)?
See this thread for further info :
http://www.sharkyforums.com/ubb/Foru.../015277-2.html
probably because the RAm sends data through the CRimms so it doesbnt amtter if it has any memory on it or not,just as long as it has to use it.
At least thats my guess https://www.sharkyforums.com/images/.../2002/02/9.gif
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I think it will not even post at just one rimm installed, even if all other slots has Crimms installed. Rdram-bus is serialised so data come in other end of rimm and keep going from other end and terminations are at the bus end in motherboard, that's why Crimms are used. To work at dual-channel mode both rdram-busses should have at least one real rimm installed. Soon there will be release of new Rimms with have two channels at one rimm and which still are compatible with older rimms.Quote:
Originally posted by Mandorallen of Molynnr:
Alright, I'm a little confused. How exactly would it be possible for the i850 to get a full 3.2 GB/s bandwidth from only one RIMM and a C/RIMM (kinda a space holder)?
There will be two RDRAM memory channels on the module. Basically all this is, is two of the old RIMMs combined into one.
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Quote:
Originally posted by Moridin:
There will be two RDRAM memory channels on the module. Basically all this is, is two of the old RIMMs combined into one.
Okay, so you are both stating that it wouldn't be possible [i]now[i]? That future RIMM's will be dual channel already - but how can these run on current slots? Wouldn't the number of pins and traces have to be increased? Would it still be 16 bit wide?Quote:
Originally posted by nakkis:
Soon there will be release of new Rimms with have two channels at one rimm and which still are compatible with older rimms.
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Duke of the OC Crusaders
System Specifications.
Sharky SETI@Home
There's empty space in middle of rimm connector, and those new rimms are probably wired so that when using two-channels the other channel is terminated in rimm, and using more than one rimm or that rimm in older motherboards it's operates just like 1-channel rimm. But that's just my guess from some specifications I have seen.Quote:
Originally posted by Mandorallen of Molynnr:
Okay, so you are both stating that it wouldn't be possible [i]now[i]? That future RIMM's will be dual channel already - but how can these run on current slots? Wouldn't the number of pins and traces have to be increased? Would it still be 16 bit wide?
I just saw the discussion in CPU/OC. https://www.sharkyforums.com/images/.../2005/06/5.gif I believe Thermo is mistaken, but I will post there.
You are correct, they would not fit in existing slots. AFAIK boards that support the new memory modules (and the modules themselves) are not available yet. I think this is a Samsung initiative, not a Rambus one.
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Life is complex. It has real and imaginary parts.