VHDL Newbie, needs help

First, this is for a homework assignment, so I am not asking for a completed project or anything.

We have to add a cache to a pipelined processor.

I think I have it working, except I cannot get the tag to be assigned. I know why, I just don't know how to fix it. I have been looking online for an example or explanation as to what to do. I understand the difference between the signal and variable, I just don't how to get around this.

cblock(153 downto 128) := addr(31 downto 6); -- set tag

cblock is a variable of std_logic_vector(154 downto 0) and addr is a signal received through the port map, std_logic_vector(31 downto 0).

So all I really have been asking is, is there a way to type cast a signal to a variable?? If so, how. If not, what can I do to perform this.

Thanks!!!!

-Tom