Interesting talk on bandwidth limitations for future multi-core scaling

Haven't read all the way through the presentation, but it seems to be the general idea is as we get larger and larger numbers of cores on a chip, as well as multi-socket configurations, we will run into bandwidth walls both on-chip and off-chip.

Thought it would be worth posting for those who are interested. Amusingly, I stumbled upon this while searching for how well Handbrake scales with multiple cores/threads, which I was looking up after noodling with the idea of picking up a new hex core CPU w/HT. (12 threads)

http://www.cs.waseda.ac.jp/gcoe/eng/...hin_Pres_1.pdf

Ignoring bandwidth issues for a moment, just getting multiple CPUs to play nice is a problem. Back in the day we called the concept -- large system effects. Or, which would you rather orchestrate pulling 500 lbs, 1,000 chickens or one elephant. Now add bandwidth to the equation and it becomes more complex.

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Originally Posted by OS-Wiz

Ignoring bandwidth issues for a moment, just getting multiple CPUs to play nice is a problem. Back in the day we called the concept -- large system effects. Or, which would you rather orchestrate pulling 500 lbs, 1,000 chickens or one elephant. Now add bandwidth to the equation and it becomes more complex.

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Do you have any interesting (and hopefully illustrated) examples of that topic? lol. It sounds intriguing, but also with the right pictures, downright entertaining.

They ran into similar problems with Larabee.

Link.

It's funny that pretty much everything that paper talks about is happening in some way. Intel is only scaling cores +50% in most systems (Gainstown to Gulftown). They're 8-core chip has a huge L3 and quad channel memory. IBM's 8-core Power7 has a massive eDRAM cache (slower, but better transistor count compared to SRAM).