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http://www.realworldtech.com/forums/...3503&roomID=11
Of course, this is coming from the same person that stated about the <70nm Leffs on AthlonXPs. Judge the credibility for yourself.
Not my opinion https://www.sharkyforums.com/images/.../2005/06/4.gif
Conrad, do you think that Ghostwhisper might be overestimating?
Arcadian
I saw those numbers and thought specint was pretty high too... don't know why...Quote:
Originally posted by Arcadian:
Conrad, do you think that Ghostwhisper might be overestimating?
Arcadian
These numbers would seem to agree with the benchmarks from that French site, so they look realistic to me. These numbers represent a 15% improvement on integer code and a 7% improvement on FP code over a 2.0GHz Willie. If anything, they seem low to me.
I have seen Ghostwhisper give out some very interesting and accurate information in the past. Take what he says with a grain of salt though, he defiantly has an Intel bias. I am about 90% certain he is an Intel engineer who works/was working on the clock distribution network for the P4.
BTW I just heard another interesting rumor over at ARS. Apparently Paul DeMone thinks Northwood has a reduces L2 cache line size of 64 bytes. Willamette has a 128 byte cache line.
http://arstechnica.infopop.net/OpenTopic/page?q=Y&a=tpc&s=50009562&f=77909774&m= 8720964033&p=2
Quote:
Roughly 10 to 12% of that 10 to 15% is from the larger cache and the
remainder is from tweaks to pipeline and accelerator block control
logic. Reportedly the L2 line size has been reduced to 64 bytes which
will help a little, especially on DDR platforms.
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Life is complex. It has real and imaginary parts.
[This message has been edited by Moridin (edited December 20, 2001).]