What's the best review?

So now that I've read most of the reviews out (except SharkyExtreme's... ahem), I can say that SimHq's got the best review. Hands down, the only thing I care about is games, and simhq put it in quick and dirty. (We of course know that 3D frame rates are largely bottlenecked by the video card, but that doesn't make the cpu irrelevant). It wasn't pretty, but as a sim nut I didn't care, I could get the information I wanted, except for Operation Flashpoint: present only in the AthlonXP review.

The thing I like most about TomsHardware's is that there are almost always enough data points where you can get a rough idea of performance scaling on benchmarks.

However, what is clear is that the benchmark makes a HUGE difference (as it always had). The AthlonXP kicks on LAME but sucks with the Microsoft encoder... The AthlonXP kicks with the Athlon optimized SeriousSam but sucks with the SSE2 optimized Incoming Forces.

If you like a lot of game benchmarks, this review has a lot.
http://firingsquad.gamers.com/hardwa...od/default.asp

Arcadian

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Originally posted by Arcadian:
If you like a lot of game benchmarks, this review has a lot.
http://firingsquad.gamers.com/hardwa...od/default.asp

Arcadian

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Ooh... firingsquad... forgot about them... xbitlabs was good too. Liked the cachemem stuff. Wonder if the write-through nature of the L1 is hurting any...

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Originally posted by Conrad Song:
Wonder if the write-through nature of the L1 is hurting any...

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Making the L1 cache "write-through" tends to increase performance, not decrease it. On the other hand, making a large level 2 or level 3 cache "write-through" would tend to decrease performance.

Arcadian

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Originally posted by Arcadian:
Making the L1 cache "write-through" tends to increase performance, not decrease it. On the other hand, making a large level 2 or level 3 cache "write-through" would tend to decrease performance.

Arcadian

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??? I would think the opposite? Unless you are effectively using write-combining to utilize the 256-bit bus to it's potential, a 32-bit write would typically just get stuck in a buffer. I would think that given the high number of memory accesses that unless you're heavily buffered, you'd strain the L1-L2 data path real fast.

Then again, a small L1 would also have a high dirty eviction rate... Makes me wonder if a large L1 like the Athlon is better, especially if hardware prefetching can bring it directly to the L1.

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Originally posted by Conrad Song:
??? I would think the opposite? Unless you are effectively using write-combining to utilize the 256-bit bus to it's potential, a 32-bit write would typically just get stuck in a buffer. I would think that given the high number of memory accesses that unless you're heavily buffered, you'd strain the L1-L2 data path real fast.

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Conrad, the Pentium 4 L1<->L2 bandwidth was designed to be both large, and taxable. By making the L1 cache Write-through, they are able to post writes directly to L2 without wasting more room in an already small L1. The only problem is if modified data is needed soon after it is written, but in that case, a mechanism called load-store forwarding is used.

Trust me: the Pentium 4 caches are designed the way they are designed because it's faster. To change a cache mode of operation is trivial; therefore, if being "Write-back" or "Write-combined" were faster, Intel would have made it that way.

Arcadian

Northwood is actually a good Pentium 4 https://www.sharkyforums.com/images/.../2005/06/5.gif But still not up to Athlon XP IMO. According to firingsquad the XP1800+ beats the 2.0A Northwood in almost every benchmark https://www.sharkyforums.com/images/.../2005/08/2.gif

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Originally posted by Arcadian:
Conrad, the Pentium 4 L1&lt;-&gt;L2 bandwidth was designed to be both large, and taxable. By making the L1 cache Write-through, they are able to post writes directly to L2 without wasting more room in an already small L1. The only problem is if modified data is needed soon after it is written, but in that case, a mechanism called load-store forwarding is used.

Trust me: the Pentium 4 caches are designed the way they are designed because it's faster. To change a cache mode of operation is trivial; therefore, if being "Write-back" or "Write-combined" were faster, Intel would have made it that way.

Arcadian

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Yeah, I shouldn't be armchair quarterbacking. I was simply speculating that the transfer request/rate for stores to the L2 have the capability of overflowing the number of available store buffers. I agree with you that my hypothesis probably is incorrect. However, I wish I had the luxury to develop and run a few architecture simulation models.

[This message has been edited by Conrad Song (edited January 07, 2002).]