Quote:
Originally posted by Moridin:
My biggest concern about Itanium is the high transistor count and large power requirements. While these are not really a problem themselves they may be indicative of underlying problems, in particular they indicate a very complex design.
As long as Itanium can be air cooled, it doesn't matter how large it is, or how high the power requirements go. In the high end server world, it's trivial to get more fans and larger power supplies.
In fact, I'm sure the general mood during design was to get high performance, even if you have to brute force it. In other words, if there is a method of getting 5% performance, but it increases the core temperature a few degrees, do it anyways. https://www.sharkyforums.com/images/.../2005/06/5.gif
From what I understand about McKinley, a smaller die size, and lower power were more of a factor in design. McKinley was also designed fairly independantly from Merced (Itanium), so there were many differences in implementations. The biggest difference was that Merced had to come out first, so a small die with lower power was less of an issue.
Quote:
Originally posted by Moridin:
I would not normally worry about a complex design but Itanium EPIC architecture is based on VLIW, and the primary goal of VLIW is to simplify the chip design. This is accomplished by using the compiler to find parallelism rather then dedicated hardware built into the chip.
This is true for VLIW, but not for EPIC. VLIW is very compiler intensive, while EPIC is a mix between compiler and hardware assisted optimizations.
Quote:
Originally posted by Moridin:
I wonder why the chip is so complex. IMHO EPIC should have resulted in simple, small, fast chip, not a large complex, slow (in MHz) chip. The other concern is, now that you have shifted complexity into the compiler from hardware it makes the compiler much more difficult to write.
Again, complexity came from trying to get the chip to debut quicker. McKinley will have a much smaller core, AFAIK.
It's also true that the compiler is tougher to write, but as I said above, there is hardware that continues to optimize the code.
Quote:
Originally posted by Moridin:
The rise if RISC architectures in the late 80's and early 90's came in large part from the recognition that careful selection of the ISA could simplify both the compiler and the micro-architecture of the processor. This resulted in better implementation of both and yielded better performance then CISC processors, even though the CISC processors had more powerful instruction sets.
Since then Intel has done an amazing job at keeping up and even passing most RISC architectures. The cost was that both chips and compilers were larger and harder to design then for a RISC chip of equivalent power.
Good point, and excellent observation. A chips performance can often times be in the implementation rather than the architecture.
Quote:
Originally posted by Moridin:
It remains to be seen whether the complexity of Itanium is the result of this being the first IA-64 processor, or if it indicates Intel made some fundamental mistakes when it defined the IA-64 ISA.
The IA-64 ISA began its design in the early '90s. It was created by some of the brightest minds in the industry. Chances are that the IA-64 ISA is pretty sound. The complexity of the die itself is not likely going to affect performance, in my opinion. Sure an optimized layout would be preferable, and we'll likely see that with McKinley.
