DDR for Processors

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Originally posted by elimc
One thing I'm curious about naukkis: if you don't think RAM latencies are that important, then why is the EV7 built with 8 small channels of RDRAM and not one or two large channels of RDRAM? The way the EV7 bus is designed gives me the impression that they tried to keep the latencies to a minimum.

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Maybe it's for granularity (being favourable to latency also), just as GeForce3/4 have 4 independant memory-controllers working together to have the same advantage

you can either acces multiple smaller datachunks separated over the controllers, or use them together to acces one big datachunk, depending on what you need

Quote:

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Originally posted by elimc
One thing I'm curious about naukkis: if you don't think RAM latencies are that important, then why is the EV7 built with 8 small channels of RDRAM and not one or two large channels of RDRAM? The way the EV7 bus is designed gives me the impression that they tried to keep the latencies to a minimum.

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Memory latencies eat bandwith, eg memory subsystem without latencies achieve it's theoretical bandwith, the more the latencies the more achievable bandwith suffer compared to theoretical. So latencies do matter, but you have very tiny performance advantage with same bandwith and reduced latency.

But EV7 is not like it is because that, rdram-chips are designed working independently and if you want to use one or two large channel everything needs to be redesigned. DDR-sdram have to use packed with large channels because it's have very poor and ineffective design with it's command bus, but if it's possible, like with point to point devices eg. Nvidia cards they also implement independent memory channels not for reduced latency but for more memory bandwith coming from taller memory bursts which decreases overall memory latencies.

It’s also possible that the EV7 doesn’t need the bandwidth provided by 8 RDRAM channels, and it is designed that way for other reasons. One possibility that comes to mind is the designers used 8 channels in order to efficiently support very large memory configurations rather then any particular need for that much bandwidth.

I don't have anything more to say than: Thanks guys.