Pentium 4 pros and cons

A little off the topic of the pipeline in PIV, but out of curiosity, are their technical limitations of socket 423? Why would Intel be changing the socket of the PIV so soon after it's release. Not to say that things cannot change but it is supposed to debut with the release of Foster? I do not understand this move.

Another question, will the PIV show a significant improvement with more memory bandwith, or will the dual RDRAM channel keep it happy. 3.2Gb/s is quite a bit. Looking for a flow chart for the 850 architecture as well. Any ideas?


Just a thought

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Computers run on smoke....when it leaks out, you are in trouble.

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Originally posted by Phlux:
A little off the topic of the pipeline in PIV, but out of curiosity, are their technical limitations of socket 423? Why would Intel be changing the socket of the PIV so soon after it's release. Not to say that things cannot change but it is supposed to debut with the release of Foster? I do not understand this move.

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Actually, you're not off topic at all. This topic deals with all the pros and cons of the Pentium 4 architecture and platform.

To answer your question, though, it could be any number of reasons why Intel is choosing to change sockets. One thing I do want to point out, though, is that I have yet to see an official press release stating that there will be a change in socket. The only things I have seen have been insubstantiated rumors, so I can't be sure that there will even be a change in socket. (I would really appreciate a link to verify this, if anybody has one).

Assuming that there is a change in socket, though, I would have to guess that it is probably for the following reason. Usually the same team that works on a product will not be the same team that works on that product's successor. I think that, because two different teams were working on Willamette (code name for Pentium 4) and Northwood (Pentium 4 on .13u shrink), that the requirements of the latter product was not received in time to be implemented in the first product. In other words, Willamette was being worked on first by one team, and they came up with a specification based on the requirements for the chip. Another team was working on Northwood, but before they came up with the requirements, the specification for socket 423 was probably already finished, so they created their own specification based on the new requirements. This is only my theory, but since miscommunication between the two groups can happen easily, it is a possibility.

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Originally posted by Phlux:
Another question, will the PIV show a significant improvement with more memory bandwith, or will the dual RDRAM channel keep it happy. 3.2Gb/s is quite a bit. Looking for a flow chart for the 850 architecture as well. Any ideas?

Just a thought

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RDRAM gives the Pentium 4 the same memory bandwidth as the front side bus bandwidth. Both interfaces allow for 3.2GB/s, and that allows for optimal transfers. It is doubtful that a different amount of memory bandwidth could allow for a better performance. My opinion is that DDR memory may in fact reduce the performance of the Pentium 4, since the bandwidth for PC2100 is only 2.1GB/s. Of course, we will have to wait until there are Pentium 4 boards with different memory interfaces to compare the two.

Also, the flow chart for the i850 will probably be very similar to other Intel chipsets, with the only exception being the dual memory interfaces.

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Originally posted by Arcadian:
[B]Hmm... I'm wondering what you're getting at here. Can you explain further, because your idea intrigues me.B]

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I'm not quite sure either. It's just that some things don't look like they should. The AGU is double pumped, so the processor can generate addresses for two loads/stores each clock cycle. The Load Store unit is not double pumped so it can only actually perform one load per clock. If the D cache was duel ported the processor could perform 2 load/stores per cycle just like the Alpha and Athlon but it is not (apparently there are a number of restrictions in the Athlon duel ported cache)

At the same time the D cache data path is twice as wide as it should be. Why would you have a 128 bit wide data paths to the L1 data cache when you can only load 32 bit integers and 64 bit floating point values?

There are a couple of possible answers. The first would be that that the 128-bit data path could be associated with SSE2, and the AGU is double pumped so that the address is ready 1/2 clock cycle sooner giving your cache extra time to return a value. I think this may be too much coincidence. Why would you have an AGU and D cache data paths that can support loading 2 64-bit numbers and build a load store unit that can only load 1 64 bit number.

Another more intriguing answer would be that the P4 can load/store 2 values per clock as long as the values were in the same 128-bit section of memory.

Or maybe Intel has some surprise in store for us.

The only reason I can think of for having the L2 bandwidth that the P4 does is so that L1 line fills occur more quickly. This would reduce latency if you had to loads that occur near each other that miss L1 and hit L2. The P4 L2 can fill the 128 Byte cacheline in 4 cycles, so you may save a few cycles of latency on occasion. My question is if this is enough to justify the L2 bandwidth.

As I said before, the P4 L2 has nearly twice as bandwidth as the core can use, so there may be something strange here as well.

I have a few minutes so I'll try to cover my opinions on a few more points.

- High Clock Frequencies

High clock frequencies are a very good thing, not everything but probably the most important. A lot of people around the web like to say clock speed is not everything and then infer that IPC is. I disagree with this, especially in X86.
The limited number of registers in the X86 architecture mean that it has to perform a lot of loads and stores compared to other architectures. IMHO this tends to make the code more linear and less suitable for executing a lot of instructions in parallel. The loads cause an even bigger problem since you can't perform calculations on data that you do not have yet. Limitations on how you can reorder loads and stores make the instruction stream even more linear.

All this combines to make it much more difficult to get IPL out of the X86 architecture compared to other newer architectures. You can get around some of this by using low latency caches, large OOO windows, and even by reducing Read after write dependencies (all of which the P4 has) but in the longer term the only way of increasing performance beyond a certain level is increasing clock speed.

(Ok more registers would be the real long-term answer but that would likely require new modes, OS support, and rewriting software. AMD has the right idea here in combining this change with the move to 64 bits. I'm not sure if AMD can get the market support this would require though, especially when you consider how long the move from 16 to 32 bits has taken and that is not even done yet.)

Higher clock frequencies have other good effects as well. Even where the P4 has increased latencies and stalls in terms of clock cycles the real latency (and performance lost) in terms of time is likely reduced because each clock cycle is shorter.

- Higher Clock Frequencies in the Future

It should be apparent by now that I think the P4 will prove to be much better than many people think. I think Intel has done an excellent job of targeting it to its intended market over its entire life span, and I think this is another example.

The pipeline of the P4 apparently has several stages with NO logic whatsoever. This is to allow signals to travel form one part of the chip to another. Now, this is a large chip, but not that large. The die itself will likely be 40 % wider and 40 % longer then the PIII, so it is unlikely that any wires are more then 40 % longer and in fact if Intel has done a really good layout job the wires may not be any longer then the PIII. So why do you need these "Drive" stages in the pipeline?

I think they are there to accommodate changes in process technology over the next few years. Right now we are on the verge of a fundamental change in the way processors speed reacts to a die shrink. A process shrink speeds up transistors, but not the wires. Up till now this has not mattered much since the wires were much faster then the transistors. We have now reached the point where the speed of the wires is often more important then transistor speed. Cu wires and SOI act as a one time speed up for the wires but this only pushes back the problem a little, it does not solve it.

I think these "Drive" stages will make the P4 much more scalable on future process shrinks then processors that do not have this type of a stage. In other words I think the P4 will get a better clock boost going from .13 Cu process to a .1 Cu (and smaller) process relative to the Athlon of PIII. It should also make it less sensitive to running on a .18 Al process, so don't be surprised if the PIII moves to .13 Cu before the P4.

Well I think that’s enough for one post, again any comments would be welcome.

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Originally posted by Moridin:
I'm not quite sure either. It's just that some things don't look like they should. The AGU is double pumped, so the processor can generate addresses for two loads/stores each clock cycle. The Load Store unit is not double pumped so it can only actually perform one load per clock. If the D cache was duel ported the processor could perform 2 load/stores per cycle just like the Alpha and Athlon but it is not (apparently there are a number of restrictions in the Athlon duel ported cache)

At the same time the D cache data path is twice as wide as it should be. Why would you have a 128 bit wide data paths to the L1 data cache when you can only load 32 bit integers and 64 bit floating point values?

There are a couple of possible answers. The first would be that that the 128-bit data path could be associated with SSE2, and the AGU is double pumped so that the address is ready 1/2 clock cycle sooner giving your cache extra time to return a value. I think this may be too much coincidence. Why would you have an AGU and D cache data paths that can support loading 2 64-bit numbers and build a load store unit that can only load 1 64 bit number.

Another more intriguing answer would be that the P4 can load/store 2 values per clock as long as the values were in the same 128-bit section of memory.

Or maybe Intel has some surprise in store for us.

The only reason I can think of for having the L2 bandwidth that the P4 does is so that L1 line fills occur more quickly. This would reduce latency if you had to loads that occur near each other that miss L1 and hit L2. The P4 L2 can fill the 128 Byte cacheline in 4 cycles, so you may save a few cycles of latency on occasion. My question is if this is enough to justify the L2 bandwidth.

As I said before, the P4 L2 has nearly twice as bandwidth as the core can use, so there may be something strange here as well.

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Well, you certainly seem to know a lot about the Pentium 4 architecture, Moridin! I was wondering about what you said, and it struck me that one possibility is that Intel included these high bandwidths for future tweaking inside the core.

Maybe they wanted some features that weren't able to be implemented on time, so they left room to implement them in a future P7 microarchitecture. Perhaps Foster or Northwood will include some surprises.

I have a few questions fot you, though. What do you think is the impact on these specs for the L3 cache that Foster is reported to have? Also, how would these specs allow for future technologies, such as multithreading, to be implemented in some later P7 based processor?

Again, thanks for the response. https://www.sharkyforums.com/images/.../2005/06/5.gif

PS... I've been meaning to ask you about your screen name. I am playing Baldur's Gate 2, and if you attack dwarves, they will shout, "By Moridin's Hammer!" Just wondering if that's where you got the name from (not the game, but the same mythical reference that the game is using).

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Originally posted by Moridin:
I think they are there to accommodate changes in process technology over the next few years. Right now we are on the verge of a fundamental change in the way processors speed reacts to a die shrink. A process shrink speeds up transistors, but not the wires. Up till now this has not mattered much since the wires were much faster then the transistors. We have now reached the point where the speed of the wires is often more important then transistor speed. Cu wires and SOI act as a one time speed up for the wires but this only pushes back the problem a little, it does not solve it.

I think these "Drive" stages will make the P4 much more scalable on future process shrinks then processors that do not have this type of a stage. In other words I think the P4 will get a better clock boost going from .13 Cu process to a .1 Cu (and smaller) process relative to the Athlon of PIII. It should also make it less sensitive to running on a .18 Al process, so don't be surprised if the PIII moves to .13 Cu before the P4.

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Wow... I'm actually glad someone brought this up. As you mention above, clock speeds will become much more fundamental to a fast processor in the future than what we have right now. A year or two down the road, I expect the Pentium 4 to scale far larger than the Pentium III or Athlon. I also agree with your frequency accessment due to copper interconnects on Intel's .13u process. If the Pentium 4 is able to reach 2.0GHz on aluminum, I imagine it can gain amazing momentum on copper. My understanding concerning SIO, though, is that Intel is cautious about using this. At one point (and I can't remember where), Intel said that SIO can do much less for their future processes than it can do now. That means it wouldn't be worth implementing, since future processes will not gain too much of a benefit. Very good post, Moridin!

It's a hobby more then anything else; I don't work in the industry so you shouldn't take anything I say as absolute fact. I have an EE background but have mostly worked in IT (information technology, not "it") since I graduated. Processor design was always my favorite topic, but any real knowledge I have is largely outdated since I studied it in the early to mid 90's and a lot has changed since then.

The P4 caught my attention with some interesting design features (many of which you mentioned) that got me interested in finding out anything I can about it (which really isn't much).

Maybe there are unimplemented features, or maybe Intel is hiding some of the real features. Have you read Paul DeMone's recent comments about P4 "Dark transistors" over at aces? He seams to feel that the feature Intel has told us about doesn’t account for the number of transistors in the core. Not to long ago I was looking at a floor plan for the chip (I can't remember where I saw it) and was struck by the amount of space that simply wasn't labeled, so maybe he is correct.


To me, the P4 L2 has a lot in common with a L1 unified cache. In fact it probably has a lower real access time then the PA-RISC L1 unified cache. If you look at it this way, with the L2 acting more like a L1 unified cache and the L1 D cache acting more like a buffer to speed up this L1 in the most common situations, adding L3 now makes a lot of sense. This is especially true if you can add L3 in the same way the as the Xeon with its large, full speed on package L2.

I am taking my name from Robert Jordan's Wheel of Time series. RJ does use a lot of mythical references in this series. In fact this is worked into the story line to a large degree, so it wouldn't surprise me to see other uses of the name in fiction and mythology. (In WOT world time is kind of circular so that we see elements of our myths in things that are happening in the story and you can even recognize some our world in their myths if you look carefully.)

Moridin is one of the chief bad guys in the series. I was a little uncomfortable with this since some people may interpret this to mean my intention was to be a troll, but the bad guy's have all the cool names and I figured my posts would speak for themselves. (In WOT Moridin = death in "the old tongue")

All in all WOT is one of the best series out there if you like this genre. It's very long though (nearing 10,000 pages and not done yet) and all one story so you can't read the books independently.

/WOT Plug

Moridin, can you please post an email address so that I can contact you privately. There is something I'd like to tell you without making it public.

Also, I enjoy the WOT series, but it has been a year or so since I have read the last book. I am very much looking forward to "Heart of Winter" coming out this month. But I forget who Moridin is. Was he a Forsaken? I think the Forsaken had all the coolest names. Asmodean was my favorite https://www.sharkyforums.com/images/.../2005/06/5.gif.

size of the level 1 cache was intentionally kept small to make 2-cycle latency possible. Low latency cache is key to keeping the pipelines well-fed. As core frequency scales higher, the limiting factor might become the double pump'd ALU. Distributed clock signals is another neat feature.

P4 really represents a different design philosophy from K7. Many trade-offs were made to achieve high MHz. I do believe in terms of ipc, K7 will come out ahead. However in its current form, the rather simplistic branch predictor is seriously hampering its performance potential. I hope mustang will rectify that problem. That said, the next major performance boost will come from integrating memory controllers on-chip. This is drastically reduce the system memory latency issues. And then the multiple core on the same chip and what not will keep the Moore's law valid for a while to come.

peace

about those drive stages, I think they are there to account for the propogation delay. Seriously the signals strength probably needs boosting travelling from one end of the die to the other. Sorta like the repeater stations for optical network. Nov. 20th is the D-day, we will all know for sure how P4 performs then.

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Originally posted by Arcadian:
Moridin, can you please post an email address so that I can contact you privately. There is something I'd like to tell you without making it public.

Also, I enjoy the WOT series, but it has been a year or so since I have read the last book. I am very much looking forward to "Heart of Winter" coming out this month. But I forget who Moridin is. Was he a Forsaken? I think the Forsaken had all the coolest names. Asmodean was my favorite https://www.sharkyforums.com/images/.../2005/06/5.gif.

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Sorry I took so long to answer, I had a busy weekend and didn't get a chance to go online. You can email me at [email protected].

As for the WOT question, I'll start a thread in off topic if there isn't already one there.

Hopefully I can finish all the points; it's taken me 3 long posts so I hope people will have been able to read them without falling asleep.

- Excellent Branch Predictor

An absolute requirement with the long pipeline. It is also interesting that it looks like the P4 has 2 branch predictors that work in co-operation. One before the trace cache and one after.

- Small L1 Cache

I like to think of the P4 L1 D cache more as a buffer for frequently accessed data. This only works if you have a very fast inclusive L2, which it looks like the P4 has. (6 cycles ???) This gives you the best of both worlds, high speed L1 and high global hit rate.

- Trace Cache

This is the key design feature of the architecture IMHO. Everything else works around it. This is a big step forward for X86 processors, and brings them one step closer to RISC like performance.

Traditionally the biggest problem with CISC processors is the large, complex decoder that is required. With the trace cache the decoder is no longer in the critical path and is no longer a performance bottleneck in most cases.

In the future it may even be possible to get some benefit from making the decoder more complex, this is unheard of without a trace cache. For example the trace cache could also allow you to optimize code on the fly and even run multiple ISA's on a single core. It already allows some optimization like loop unrolling.

I also see a big parallel with Transmeta's "code morphing software". If you think about it, the trace cache is almost the same thing as code morphing, only it is done it in hardware and therefor is much faster.

- Large # of Instructions in Flight

The more instructions in flight the more ILP you can get and the higher you IPC. The only downside is that complexity grows quickly as you have more instructions in flight and the returns tend to drop off. Modern production processes allow for many more transistors in a processor core and this is one very good way to put those extra transistors to work.

- New PC Specification / Large Heat Sinks

I remember when the P5 first came out and people didn't like the fact that it often needed a fan. This is something that people will get used to. I do find it interesting that the P4 can still use passive cooling in some cases.

I wonder where this is going though. I remember in 1995 looking at some projections for chip power and speed and seeing desktop chips using 100 W by 2005 and 1000 W by 2015. I thought "no way they will make them work", clearly I was wrong. Think about it though, 100 W is a light bulb and 1000 w is a toaster!!!

- Low Expectations (on Websites)
- Rumors on the Web

People like to speculate; I see nothing wrong with that. It won't change the final results.

- i850 Delays

Better to have a short delay then risk problems after release. P4 production still continues so this may not even change the number of P4's sold this year. It may just increase availability on release.

- Price Issues

Market and economic conditions drive price. Even Intel only has a limited say on the selling price. For a long time, resellers were charging much more for the 1 GHz PIII then Intel was just due to its limited availability.

- Much More!

What can I add here, you covered just about everything. Hardware prefetch is about all I can think of to add.

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Originally posted by theorcus:
about those drive stages, I think they are there to account for the propogation delay. Seriously the signals strength probably needs boosting travelling from one end of the die to the other. Sorta like the repeater stations for optical network. Nov. 20th is the D-day, we will all know for sure how P4 performs then.

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Yes, I'm sure that is what they are for. He question is why. The P4 may be twice as large as the PIII in area, but that only translates into about 40 % longer per side. Signal paths were not as important when the PIII was designed as they are now and not nearly as important as they are likely to become.

No P4 designers might have been able to keep these paths to PIII levels with careful design, instead they chose to use drive stages. I think they did this to allow the processor to run well on future processes where long signal paths would prevent process shrinks unless a drive stage was included.

In other words Intel was really planning ahead.

I think the P4 will prove to be an excellent design in its intended market. Every processor design (or any other design for that matter) is a series of give and take. Most changes will not be universally good; they will help one thing but may hurt another. Success or failure is often a matter of optimizing for the right thing.

For example optimizing the P4 for Word likely would have been a mistake, since Word runs fast enough on just about anything. Gaming on the other hand will almost always use all the processor power it can get. If it came down to a choice between something that improved performance in Word and something that improved gaming then Intel almost certainly emphasize gaming.

I think the P4 will be particularly good at things like games, 3D graphics/eye candy, streaming media applications, and voice recognition. In other words it will be very good at things the typical home user/desktop user is interested in. On the other hand it may fall down a little on Workstation and server type software in professional/CAD and transactional database apps.

I think this is a strong possibility since this is the market IA-64 was supposed to compete in. It seems likely to me that this type of application received lower priority when optimization was considered.

For example if they wanted to compete strongly in the Workstation market they would have concentrated on making X87 much better, of even implanted a RISC like technical floating point instead they concentrated on SIMD which is more suited to consumer software.

Similarly, If they were hoping to concentrate on transactional database work they would have kept the pipeline as short as possible since that type of application consists of hard to predict branches. I expect the P4 to be a poor performer clock for clock on Oracle databases because of this. I don't know if the high clock speed will make up for this or not.

The more I think about it the more it seems to me Intel really did their homework and that the P4 is going to excel at processor intensive consumer apps we will se over the next five years. High end Workstation apps and Server apps may be a different story.

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Originally posted by Moridin:
Sorry I took so long to answer, I had a busy weekend and didn't get a chance to go online. You can email me at [email protected].

As for the WOT question, I'll start a thread in off topic if there isn't already one there.

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Thanks. I read your last comments, and it seems pretty solid. I think I agree with what you say, and I think that the Pentium 4 will be more of a future looking product. We'll have to see how well it performs at launch, but I'm willing to believe it should do pretty well.

By the way, I did email you. Check your email if you haven't already https://www.sharkyforums.com/images/.../2005/06/5.gif.

Arcadian thanks for the link to the pdf file, i also had a busy weekend, will have to read it tonight.

Hey arcadian two great posts this one and the bottle neck one........

just a little off topic in regard to the amd intel thing i think it will be a long time before we see amd take intels crown.....I mean we're all well I won't say geeks lets say extremely computer literate and we know enough to look at the benchmarks now but the average user goes for an established name ie intel and its this market which intel has conered the compaq, dell, gateway, ibm, hewlett packard, packard bell etc and it will be a while before amd can take over such an established market

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'From now on I'm thinking only of me.'

Major Danby replied indugently with a superior smile: 'But, Yossarian, suppose everyone felt that way.'
'Then,' said Yossarian, 'I'd certainly be a damned fool to feel any othe way wouldn't I?'

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Originally posted by colonel:
Hey arcadian two great posts this one and the bottle neck one........

just a little off topic in regard to the amd intel thing i think it will be a long time before we see amd take intels crown.....I mean we're all well I won't say geeks lets say extremely computer literate and we know enough to look at the benchmarks now but the average user goes for an established name ie intel and its this market which intel has conered the compaq, dell, gateway, ibm, hewlett packard, packard bell etc and it will be a while before amd can take over such an established market

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Thanks for the reply, and also for the complement, colonel. I think AMD has the speed race covered right now with their Athlon + DDR, but in the spirit of this topic, I don't want to speak too soon. The Pentium 4, while fundementally flawed in some areas, is immensely powerful in others. I accept these tradeoffs as educated engineering decisions. I have the feeling the Pentium 4 will offer more performance, and much more scaling, than the Athlon processor can.

Ultimately, however, I believe the real winner is who can produce more product. Right now, and in the foreseeable future, that is Intel. AMD is doing well, though, and has increased capacity in their two fabs to help produce more than they ever have before. They are also selling very well.

In terms of growth, though, AMD is not likely to grow much as a company unless they quit with their price wars. They can afford to price their products lower, because of the fact that they can produce more, but you can't grow as a company if you're only breaking even. Maybe this is ok for AMD, but Intel is still interested in growing with the industry, I believe, which is why they are very concerned with increasing their own fab capacities. When Intel reaches .13u, and they ramp up on Pentium 4, AMD will have need to worry, I believe.

I have read the explanations of pipelining and followed the links to G4 thread and hardware centrals explanation. They have all been great, and I think I now have a pretty good grasp of it. But I dont understand one thing. The P3 at .18 micron can reach a max of about 1.13 GHz. The P4 at .18 micron is apparently not going to be much good because at max speeds of 1.4/1.5 GHz, the branch mispredictions will slow it and the advantages of the larger pipeline comapered to the P3 won't be realised at those speeds.

What I dont understand is that if the P4 has a pipeline of double the size, essentially cutting work of each stage in half, allowing a clock cycle to take half as long as the P3, why then is the max speed of the P4 at 0.18 micron 1.4/1.5 GHz and not 2.26GHz???

Oh wait, an idea just came to me. Because you have double the pipelines and so therefore approximately double the resistor count requiring double the amount of power to run, does this make the chip too hot to run stablely at anything past 1.4/1.5 GHz?? If this is the case then wouldnt Intel have made a mistake with these extra pipe stages, because even though they can theoreticaly run at double the speed of a P3, the extra heat caused only allows a clock improvement of about 25%, and maybe not worth extra cost in doubling the die size req'd for a chip. Or will the heat scale with the die shrink, allowing a .13 P4 to have 50% max clock increase over a .13 P3. (Intel reckons P3's will reach 2 GHz on .13 micron)?

Don't worry, Floyd, the 1.4GHz and 1.5GHz speeds of the Pentium 4 are only launch speeds. Some Intel roadmaps released on the web indicate that the Pentium 4 will reach 1.7GHz before March, and 2.0GHz before June, and all this on .18u process. Intel's 130nm process will probably be able to get to nearly 3.0GHz once it is fully optimized. Make no mistake: the Pentium 4 was made for speed. https://www.sharkyforums.com/images/.../2005/06/5.gif

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Originally posted by Floyd:
I have read the explanations of pipelining and followed the links to G4 thread and hardware centrals explanation. They have all been great, and I think I now have a pretty good grasp of it. But I dont understand one thing. The P3 at .18 micron can reach a max of about 1.13 GHz. The P4 at .18 micron is apparently not going to be much good because at max speeds of 1.4/1.5 GHz, the branch mispredictions will slow it and the advantages of the larger pipeline comapered to the P3 won't be realised at those speeds.

What I dont understand is that if the P4 has a pipeline of double the size, essentially cutting work of each stage in half, allowing a clock cycle to take half as long as the P3, why then is the max speed of the P4 at 0.18 micron 1.4/1.5 GHz and not 2.26GHz???

Oh wait, an idea just came to me. Because you have double the pipelines and so therefore approximately double the resistor count requiring double the amount of power to run, does this make the chip too hot to run stablely at anything past 1.4/1.5 GHz?? If this is the case then wouldnt Intel have made a mistake with these extra pipe stages, because even though they can theoreticaly run at double the speed of a P3, the extra heat caused only allows a clock improvement of about 25%, and maybe not worth extra cost in doubling the die size req'd for a chip. Or will the heat scale with the die shrink, allowing a .13 P4 to have 50% max clock increase over a .13 P3. (Intel reckons P3's will reach 2 GHz on .13 micron)?

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Intel has already demonstrated a 2.0GHz P4 made in .18 Aluminum, so like Arcadian said the 1.4/1.5 is just the initial speed. AFAIK the PIII didn’t go above 733 MHz on this process initially.

It is quite possible to double the length of a pipeline and not double your clock speed for a few reasons. The first is if you add additional logic to the pipeline. This would make your processor clock more slowly but would improve your IPC since the additional logic would be there for a reason.

The second possibility is that the pipeline is not balanced. If you split every stage in half except for the longest one you clock speed will not increase at all. I doubt that the P4 has a problem in this regard. If it fails to run twice as fast as the PIII it is because Intel has added additional logic.

One more thing I thought I would point out is that the P4 actually has 26 pipeline stages when you count the decoder. The 6 stages in the decoder only come into play if you have a trace cache (L1 I cache) miss since the trace cache holds decoded instructions.

Do not assume that the benchmarks you have seen reflect the real performance of the chip. The improved branch predictor should be enough to offset the branch penalty of the longer pipeline and the P4 is as good or better then the PIII in every other area. I can’t see the P4 performing worse then the PIII clock for clock on anything but legacy code or code with impossible to predict branches.

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Originally posted by Moridin:
One more thing I thought I would point out is that the P4 actually has 26 pipeline stages when you count the decoder. The 6 stages in the decoder only come into play if you have a trace cache (L1 I cache) miss since the trace cache holds decoded instructions.

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That's true, but did you know that there are even more stages than that? The 20-stage pipeline is only a best case scenario. I don't know the max amount of pipeline stages, but I bet it is well over 26. https://www.sharkyforums.com/images/.../2005/06/5.gif

First I'd like to say that it's nice to see a microarchitecture discussion without a lot of rhetoric and handwaving. With that said I'll add my 2 cents.

Arcadian mentioned a while back about the package change for the P4. The primary benefit of moving from a 423 pin to a 478 pin package will be power delivery. I/O receives no benefit, but with the addition of more power and grounds Intel can better balance their power planes.

This will result in lower power requirements and less noise. In addition to the Northwood processor there will also be a Willamette-478 to ease transitional issues.

The cache lengths were also mentioned earlier. I like the bandwidth availability with 256-bit cache lines, and especially the fact that L2 can load one cache line each clock, versus every other clock for a PIII.

The only downside to this that I can see is latency. 256-bits must always be fetched from memory even if a smaller amount it needed. Yet again we are faced with one of those tradeoffs geared toward high bandwidth applications. In the long run it will turn out to be the right decision, but it also explains why new processors won't always lead in every benchmark even if they are capable of much higher performance.

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Originally posted by Marsolin:
First I'd like to say that it's nice to see a microarchitecture discussion without a lot of rhetoric and handwaving. With that said I'll add my 2 cents.

Arcadian mentioned a while back about the package change for the P4. The primary benefit of moving from a 423 pin to a 478 pin package will be power delivery. I/O receives no benefit, but with the addition of more power and grounds Intel can better balance their power planes.

This will result in lower power requirements and less noise. In addition to the Northwood processor there will also be a Willamette-478 to ease transitional issues.

The cache lengths were also mentioned earlier. I like the bandwidth availability with 256-bit cache lines, and especially the fact that L2 can load one cache line each clock, versus every other clock for a PIII.

The only downside to this that I can see is latency. 256-bits must always be fetched from memory even if a smaller amount it needed. Yet again we are faced with one of those tradeoffs geared toward high bandwidth applications. In the long run it will turn out to be the right decision, but it also explains why new processors won't always lead in every benchmark even if they are capable of much higher performance.

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Thanks for the complement. I think this topic has a lot of insight as well, and I appreciate the technical aspects.

My one comment about you post is concerning the last paragraph. I don't believe the cache will ever transfer less than 256 bits of data. The reason being is that the Pentium 4 uses 128 byte cachelines, and will always transfer that amount of data. Using a 256 bit datapath, that means it takes 4 ticks of the 1.5GHz Pentium 4 clock to transfer the cacheline, and it should always take that long. In this case, the 256 bit wide datapath is a completely necessary addition.

I know many of you guys are PC gamers but if you look at discussions going on right now amout the Sony PS2 they are very similar to this one in a way I have noticed.

Whats my point?
Sony and Intel have made similar decisions in hardware design for their respective systems.
How?
The very small, but EXTREMELY fast caches and increased memory bandwith. A twist from the tradition of large caches with slow bandwiths and long latencies.

If you think about it this is a very smart move as more games and apps demand fast streaming info, not recuring large chunks of info.

Just my take.