Northwood versus Palomino: Place your bets!

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Originally posted by ynd69:
Agreed.

I just hope Tbred comes with 512k L2 cache and an official 166FSB...that would be sweet.

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Unfortunately, all roadmaps to this point show that T-Bred will not gain any such changes. They are still slated for 256K L2 cache and a 266MHz FSB. The only changes will be full .13u manufacturing.

Mind you, this is according to the roadmaps, which do have a tendency to change.



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Earl of the OC Crusaders

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Originally posted by talldude:
And hey, while we're at it, let's not forget Hammer debuting at XP4400...I'm already salivating... https://www.sharkyforums.com/images/.../2005/06/4.gif

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Don't you mean 3400?

Arcadian

Quote:

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Originally posted by Un4given:
Unfortunately, all roadmaps to this point show that T-Bred will not gain any such changes. They are still slated for 256K L2 cache and a 266MHz FSB. The only changes will be full .13u manufacturing.

Mind you, this is according to the roadmaps, which do have a tendency to change.

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My personal prediction, given the facts and some common sense, is the following.

Regarding the 512KB of L2 cache, I don't see why AMD wouldn't implement this. If not in TBred, they certainly would in Barton. The die size is already small, and some web forums have shown that it is even possible to fit 512KB of L2 in a TBred die size of 80mm^2. AMD is usually quite adamant about maintaining performance superiority over Intel, so it seems like they'd go the extra mile to add the cache.

Regarding 333MHz front side bus, I doubt it. Any change in the front side bus speed requires a change in infrastructure for the platform. The chipset will need to support it, and AMD will have to introduce a new line of 333MHz based processors. Since they have Hammer as arriving in Q4, it seems like they can wait on the front side bus improvement (since Hammer will have a 400MHz equivalent Hypertransport bus).

So in my opinion, 512KB of L2 is in, and 333MHz front side bus is out. Of course, I could be wrong.

Arcadian

Quote:

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Originally posted by Arcadian:
My personal prediction, given the facts and some common sense, is the following.

Regarding the 512KB of L2 cache, I don't see why AMD wouldn't implement this. If not in TBred, they certainly would in Barton. The die size is already small, and some web forums have shown that it is even possible to fit 512KB of L2 in a TBred die size of 80mm^2. AMD is usually quite adamant about maintaining performance superiority over Intel, so it seems like they'd go the extra mile to add the cache.

Regarding 333MHz front side bus, I doubt it. Any change in the front side bus speed requires a change in infrastructure for the platform. The chipset will need to support it, and AMD will have to introduce a new line of 333MHz based processors. Since they have Hammer as arriving in Q4, it seems like they can wait on the front side bus improvement (since Hammer will have a 400MHz equivalent Hypertransport bus).

So in my opinion, 512KB of L2 is in, and 333MHz front side bus is out. Of course, I could be wrong.

Arcadian

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While I agree that the platform would need to be modified, I think I would venture to say that the only thing really required is for chipset makers to include an appropriate AGP divider.

My guess is that the current chipsets are more than capable of running properly at a 166MHz bus speed, and the reason most people don't obtain such o/c is because of RAM not being certified for that speed, or their AGP/PCI devices start choking out on the o/c PCI/AGP busses.



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Earl of the OC Crusaders

P3 700@980 (140x7.0 1.85V--dropped from 1001 to o/c video higher)
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Quote:

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Originally posted by Un4given:
While I agree that the platform would need to be modified, I think I would venture to say that the only thing really required is for chipset makers to include an appropriate AGP divider.

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It's not about the hardware capability - like you say, it's practically already there. It's about the expense of supporting a number of new configurations that AMD would probably want to avoid. If Hammer is really less than a year away, why introduce a new line of products that will need support, when they can simply wait a little longer? Just my opinion.

Arcadian

Quote:

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Originally posted by Arcadian:
It's not about the hardware capability - like you say, it's practically already there. It's about the expense of supporting a number of new configurations that AMD would probably want to avoid. If Hammer is really less than a year away, why introduce a new line of products that will need support, when they can simply wait a little longer? Just my opinion.

Arcadian

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Well, they could always limit it to one line. Offer an XP version with a 512K cache and 166MHz DDR FSB. This could become their new flagship, and could carry a nice little premium that could help them make some money.

The die manufacturing wouldn't change for a FSB change, it only affect the process at the level where the die is mounted to the OPGA.

I personally think AMD would be better off doing this vs. a 512K cache. The reason being, it you look at scaling, the Athlon does much better with FSB scaling. If you compare a Duron to the Athlon at the same FSB, there is not much difference except in programs where the data sets don't seem to fit into the Duron's substantially smaller 64K L2 cache. Right now, most data sets seem to fit OK into the 256K cache of the Athlon, P3, and P4 procs.

However, you are right in the perspective of it being harder to get full implementation of the platform for a bus increase. AMD would had to have notified the chipset vendors of their intentions, and given those manufacturers time to test and validate proper operation at that speed, plus the lead time to board makers to test and validate their designs and implementation. Adding another 256K of L2 cache would not require anything on the part of chipset or board makers.



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Earl of the OC Crusaders

P3 700@980 (140x7.0 1.85V--dropped from 1001 to o/c video higher)
Abit VH6-II w/256MB PC150 (2-2-2)
Radeon 64MB VIVO 205/205
SBLive! Value
13.5GB & 30GB Maxtor ATA100 (5400RPM)
Memorex 36X CD-ROM/TDK 8x4x32 CD-RW