Northwood is here...oh boy, so what??!!

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Originally posted by talldude:
to put it very simply, the P4 architecture is much more scalable (you can increase operating frequency more easily) than the athlon XP architecture. Many factors contribute to this...maybe a better post for high tech guys to handle https://www.sharkyforums.com/images/.../2005/06/5.gif

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You don't have to be a high tech guy to answer that question! ( not that i am no high tech guy https://www.sharkyforums.com/images/.../2005/06/5.gif )

Anyway it is rather simple: increasing frequency will increase heat output and that is something that is somewhat of a problem with CPU's unless you go with finer manufacturing methods like .13u or what amd will soon use : SOI Silicon On Insulator , these methods decrease heat output and icrease the frequency at which the chip can operate.

AMD now has the ability to relase faster chips but that way they would not have anything more to relase in the future so they phase their relase scehdule out so that they can release new CPU's over a long periond of time.

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No, you're wrong.

In some countries (according to CNBC market watch), such as Japan, AMD already possesses nearly 50 % of the market shares.

Worldwide, AMD is beginning to make INTEL chew its fingernails, with something like a 40% market share.

So I'd say it's not a marked domination. More like a trembling domination.

It seems AMD is on the right track. Let's hope it continues that way.

Chronus www.sim-news.com
Sim-News Contributing Editor

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Originally posted by CJ8879:
[B...
[/B]

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Originally posted by Chronus:
No, you're wrong.

Worldwide, AMD is beginning to make INTEL chew its fingernails, with something like a 40% market share.

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AMD claims 25% of the desktop market, Intel claims high seventies for overall processor sales. The 40% number may be realistic or even low if you exclude tier 1 vendors like Dell, Compaq, IBM etc. AMD still has almost no sales in the largest segments of the desktop market. (Corporate, government, large OEM sales to consumers (like Dell) etc)

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Life is complex. It has real and imaginary parts.

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Originally posted by morphid:
ok. we all know that with the xp's quantispeed architecture, the IPC is 9, whereas the p4's is 6. is this also the case with the northwood core? (i'm no intel expert). another thing that i just don't understand: if intel can increase their operating frequency so much without increasing their IPC, why can't AMD just go ahead and do it? AMD state:

performance = IPCxFrequency

that's all well and true, but if they increase the frequency to the level that intel has, then they would whoop arse even more, not true? help me out here!

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Performace = # of instructions in the code path/(IPC * MHz)

not

IPC * MHz

You do no that IPC has nothing to do with peek throughput right?

The numbers I have seen indicate that, on average, most X86 processors execute around 1 X86 or X87 instruction or around 1.5 micro-ops/risk ops per clock. Even the 486 was close to this mark.

This is what IPC is. You run a specific program, count the instructions that were executed and divide by the time in seconds. It has nothing to do with how many execution resources the processor has.

For a quick comparison, in one clock cycle, the AXP can theoretically execute:
3 Integer instructions
3 loads/stores
1 FP add or subtract
1 FP multiply or divide
1 FP load/store


The AXP has a semi dual ported L1, so it is really limited to 1 or sometimes 2 64-bit load/stores per clock, no matter what the internal execution resources seem capable of.

The P4 can execute

4 integer instructions
2 Integer load/stores
1 FP load/store
1 FP instruction (Add, subt, multiply, or divide.)

I forget whether SSE2 instructions can be mixed with X87 instructions, but I don’t think they can. With SSE2 this changes to

4 integer instructions
2 Integer load/stores
2 SSE2 load/store
4 single precision FP operations
or
2 Double precision FP operations

The P4 has a single ported 128-bit L1 access, so it is limited to a single 64-bit or a single 128-bit load/store per clock regardless of the throughput of the load store units.

(I was working from memory, and didn’t go back to data sheets to confirm these numbers. Some may be a little off, if they are please feel free to correct me on them.)


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Life is complex. It has real and imaginary parts.

Please incorporate the SSE-equivalent (3D Now! enhanced) to that "theoretical" capability of the AXP. It's easy to make these figures appear out of linear reasoning.

Chronus
PS: I will not explain it in detail as I don't remember the exact figures from AMD's papers. But feel free to object. https://www.sharkyforums.com/images/.../2005/06/6.gif

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Originally posted by Moridin:
...

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Originally posted by Chronus:
Please incorporate the SSE-equivalent (3D Now! enhanced) to that "theoretical" capability of the AXP. It's easy to make these figures appear out of linear reasoning.

Chronus
PS: I will not explain it in detail as I don't remember the exact figures from AMD's papers. But feel free to object. https://www.sharkyforums.com/images/.../2005/06/6.gif

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3DNow and SSE both allow 4 single precision ops per clock, neither can do double precision. (I don’t remember but 3DNow may be able to do non IEEE compliant double precision. I don’t think it does and it would be pointless anyway but it may.)

Regardless, the only time these processors will get anywhere close to these numbers or the ones above, is on specially designed synthetic code. They will never approach them on real code. (This is why synthetic benchmarks like Sandra are BAD.)

Edit
single precision is really only useful in graphics, and things like games in particular. It can be used for rendering as well, but this is at the expense of a slight reduction in image quality, so most packages use double precision for rendering.

For any scientific/technical work you need IEEE compliant double precision. X87 also supports IEEE compliant 80-bit precision, but this is rarely used since all the RISC platforms only support up to 64-bit.
/Edit


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Life is complex. It has real and imaginary parts.

[This message has been edited by Moridin (edited January 10, 2002).]

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Originally posted by talldude:
Lastly, the Northwood has several core improvements over the Williamette:
Northwood:
512Kb L2
.13u copper interconnects
improved branch prediction

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Does anybody know what the branch prediction % is of the Williamette and Northwood? I remember the P3 being around 92% or so.

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As a Software Developer, I have to agree with your reasoning. I do think 3D Now has that capability, but yes, it won't help much.

Thanks for clearing that up.

Chronus
Sim-News Contributing Editor

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Originally posted by Moridin:
3DNow and SSE both allow 4 single precision ops per clock, neither can do double precision. (I don’t remember but 3DNow may be able to do non IEEE compliant double precision. I don’t think it does and it would be pointless anyway but it may.)

Regardless, the only time these processors will get anywhere close to these numbers or the ones above, is on specially designed synthetic code. They will never approach them on real code. (This is why synthetic benchmarks like Sandra are BAD.)

Edit
single precision is really only useful in graphics, and things like games in particular. It can be used for rendering as well, but this is at the expense of a slight reduction in image quality, so most packages use double precision for rendering.

For any scientific/technical work you need IEEE compliant double precision. X87 also supports IEEE compliant 80-bit precision, but this is rarely used since all the RISC platforms only support up to 64-bit.
/Edit

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Originally posted by dudewtf:
Does anybody know what the branch prediction % is of the Williamette and Northwood? I remember the P3 being around 92% or so.

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Northwood would be the same as Willamette. There was no change to the branch prediction system.

Arcadian