Itanium - any comments?

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Originally posted by Moridin:
The number of rename registers is directly related to the number of pipeline stages. The more stages the more rename registers you need. The Athlon has 72 and the P4 has 128. I don’t know *** many the PIII has but I suspect it is about the same as the Athlon since the working parts of the pipelines are about the same length.

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Where did you get that information from?
I was unable to find any information about how many renaming register there are on the Athlon on AMD site.

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Originally posted by Humus:
Where did you get that information from?
I was unable to find any information about how many renaming register there are on the Athlon on AMD site.

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Whoops, I may have been thinking of the number of instructions in the Instruction control unit/reservation satiation. (That will teach me to post when I am drinking.) Sorry about that.

I have seen numbers in this range before for the number of rename registers though, but I can’t remember where just now. I know you need a lot more then 10 to 20 registers, 10 to 20 sets of registers (80 to 160) makes more sense to me. You may need up to 1 set of registers for each instruction currently in one of the pipelines.

I'll start with admitting that I'm not sure how the renamning actually work and I don't have any Athlon pipeline scheme in front of me now, but I don't believe in 100 renaming register.
Register renaming is only used to avoid pipeline stalls with false dependencies. First of all those aren't too many (ok, not uncommon but they are below perhaps 15% (wild guess) of the code). Anyway, we may want to avoid stalling the pipeline even in the worst case scenario which would be something like this:

ADD EAX, EXB
ADD EBX, ECX
ADD ECX, EDX
ADD EDX, ESI
ADD ESI, EDI
ADD EDI, ESP
ADD ESP, EBP
ADD EBP, EAX
...
etc.

My feeling is that you have a bunch of renaming registers, and when a write after read occurs you need to assign the register to a new renaming register for the write operation so that reading and writing to that register can occure at the same time. Now that a register is renamed the old register is free to be used for subsequent renaming operations. The worst case scenario is that all register would need to be renamed, like in my example above with a cpu that could execute 7 instructions in parallel (the last instruction has a true dependency of the first). In this case you need 15 renaming registers. Add to that the flags register + 1 for renaming for it and you have 17 registers.

[This message has been edited by Humus (edited November 12, 2000).]

I'm guessing the IA64 transition will be a lot like the Mac PPC transition way back when. Personally, I think if Intel can do a decent job of the IA64 as opposed to the early days of the P3 it will be an awesome setup that blows the doors off AMD in the high end server market.

On the other hand, this is Intel, and so I'd take everything surrounding IA64 with a hefty helping of salt.

Also, Intel does tend to overcharge for their chips and I'm confident that AMD will retain its price/performance leadership. Clawhammer looks way more feasible for the average high end user, and Sledgehammer should do well in the high end market as well because it won't have the transition problems of IA64.

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"It is better to keep your mouth closed and look stupid, than to open it and remove all doubt."

~Famous Dead Guy

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Originally posted by nukefault:
Also, Intel does tend to overcharge for their chips and I'm confident that AMD will retain its price/performance leadership. Clawhammer looks way more feasible for the average high end user, and Sledgehammer should do well in the high end market as well because it won't have the transition problems of IA64.

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No transition? Sledgehammer will have 10x the transition that Itanium will have. First, ask yourself what Itanium needs. The first answer I expect you to say is software. Now think about the transition Seldghammer needs. If you stare back at me with a blank look, I'm going to assume you don't know, so let's talk infrastructure.

* Will AMD have rack optimized servers ready from OEMs?
* Will motherboard manufacturers include 64bit or 66MHz PCI in their 760MP motherboards?
* Will AMD push forward with power and disk redundancies, as well as hot-plug?
* Will AMD's systems scale well, and include ample memory upgradability?
* Will AMD have support from major server OEM's like IBM, HP, NEC, or Compaq?
* Will AMD include ECC support for memories and caches?
* Will AMD be able to guarentee stability to increase uptime and reliability?
* Will AMD include server management features to increase servicability?

These are all transition items necessary for Sledgehammer's acceptance. AMD is not known for being a good supplier of any of them, so I have a feeling Sledgehammer will have a tough time breaking through the low end.

But, I'm glad you mentioned this, since it gave me a chance to explain about server infrastucture. Thanks for the post, nukefault. https://www.sharkyforums.com/images/.../2005/06/5.gif

I think the sledgehammer may have a hard time in the server area, but I think it may actually be rather popular in desktops if the price is compititive.

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Originally posted by Humus:
I think the sledgehammer may have a hard time in the server area, but I think it may actually be rather popular in desktops if the price is compititive.

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Clawhammer will be the processor for desktop systems, and I can safely say that you will definately NOT see Sledgehammer for desktops. AMD plans on using a ccNUMA architecture for the Sledgehammer platform, and their 4-way and 8-way systems will be very expensive. I figure $10,000-$20,000 for an entry level system (this is still higher price/performance than Intel's 4-way systems, which go from $20,000-$40,000 for "light" configurations). Clawhammer will probably go for the $2,000-$3,000 systems (performance desktop segment), so if you are looking for a K8, that should be the one you choose.