Actually, didn't the AMD K6-3s have L3 cache as well? Not sure if it was on die though, don't think it was.
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Actually, didn't the AMD K6-3s have L3 cache as well? Not sure if it was on die though, don't think it was.
Nope. The K6-3 had 512K of L3 cache way, way back.Quote:
Originally posted by Dude
"the chip would sport a 800MHz frontside bus allied to the 2.5MB L3 of cache in total."
An L3 cache? Will this be the first cpu w/ and L3 cache?
Where did you see this Prescott announcement? I looked at AT, but didn't see it. Also, I wonder if the P4XE will use the updated version of hyperthreading or the Xeon version? Hope they fixed HT on it...Quote:
Originally posted by Voodoo 5 5500
[B]If you notice at www.anandtech.com right below the new P4 announcment they have news that Prescott even with half the cache of this new P4 has more tansistors proving its going to be a major overhaul of the P4. Also they say Prescott is ready to be produced in mass and its yeilds are also high.
So it looks like Intel released this CPU not out of desperation but to win back the hardcore croud right before the scheduled presscott release(which is still on time).
I hope they leave SMP enabled imagine 2x 3.2ghz 800mhz FSB 2.5mb cache on one of those new Asus i875 boards can you say holy ****? ;)
The desperation of Intel has nothing to do with how much money they earn.Quote:
Originally posted by marv
Intel says 3rd-qtr rev to be $7.6 bln-$7.8 bln
September 04, 2003 4:21:00 PM ET
Desperation....
SAN FRANCISCO, Sept 4 (Reuters) - Intel Corp. (INTC), the world's largest maker of semiconductors, on Thursday narrowed its revenue forecast for the third quarter to between $7.6 billion to $7.8 billion, the high end of its latest forecast and even with or above what analysts expect.
On Aug. 22, Intel raised its revenue forecast to between $7.3 billion and $7.8 billion, from an earlier target of $6.9 billion to $7.5 billion. At the time, the company cited stronger than expected demand for its microprocessors, the brains of computers.
Analysts, on average, were targeting third-quarter revenue of $7.6 billion, according to Reuters Research, a unit of Reuters Group Plc.
The chip industry is seeing signs of a recovery following its worst downturn ever that came amid an economic downturn and slump in corporate spending. REUTERS
AND
SAN JOSE, Calif., Sept 16 (Reuters) - Intel Corp. (INTC), the world's largest chip maker, on Tuesday outlined plans for two new chips that will have two or more processors on a single piece of silicon, boosting the performance of corporate server computers.
The new chips are a 32-bit Xeon server processor MP, code-named "Tulsa," which will be its first dual-core chip, and a new 64-bit Itanium server chip, code-named "Tanglewood," Intel President Paul Otellini said in his keynote address at the Intel Developer Forum.
Tanglewood will come some time after 2005 and Tulsa in two to three years, he said.
In an interview, Otellini declined to say what plans Intel has for bringing 64-bit chips to PCs. Currently, its chips for PCs crunch 32 bits of data at a time.
"The production operating systems are not there yet" for 64-bit desktop computers, he said. "The mainstream applications won't exist until next year."
Intel obviously has to pull some trick to compete with the Athlon64 and now everybody knows that trick is the added 2mb of L3 cache, which is not an everyday thing to do for Intel.
Sure Intel has much more money then AMD but if AMD had 10% more market share they would have destroyed Intel, look at what Intel has to do to compete with a 15% market share holding company.
If AMD had some more money to pour into R&D Intel would have needed a 1200Mhz FSB and 4mb of L3 cache to compete, and that does not sound so ridicolous after this announcement does it?
So desperate?
uhm... Yeah think so!
Yes I do, because it is OBVIOUSLY having problems. There is no other reason for Intel to introduce a high cost, large cache processor right now. After all, the Prescott is supposed to clean house, and be their number one processor. Why would Intel then release a competitor to its own premium line.Quote:
Gosh you love to bash Prescott....
The only way this makes any sense is if Prescott is delayed and Intel needs a stop gap measure. Which this sounds like.
This is a Xeon. It costs Intel nothing in R&D, and it's production cost is still well under 100$. Even if they only sell a few of them Intel stands to make a profit, so what reason could Intel have to not produce this chip?.Quote:
Originally posted by irwincur
Yes I do, because it is OBVIOUSLY having problems. There is no other reason for Intel to introduce a high cost, large cache processor right now. After all, the Prescott is supposed to clean house, and be their number one processor. Why would Intel then release a competitor to its own premium line.
The only way this makes any sense is if Prescott is delayed and Intel needs a stop gap measure. Which this sounds like.
OEM partners should have them very soon and start shipping them in the next 30 days.Quote:
Originally posted by yiotis
Strange it's true after all.
Did they mention a release date?
Look for them in the retai lchannel after new years or maybe slightly before.
From the Inq, quoting an Intel spokesman, "The chip will be produced using .13ยต technology but will later move to a 90 nanometer process."Quote:
Originally posted by Moridin
This is a Xeon. It costs Intel nothing in R&D, and it's production cost is still well under 100$. Even if they only sell a few of them Intel stands to make a profit, so what reason could Intel have to not produce this chip?.
Moridin, I wonder if this would be a natural byproduct of moving Xeon to 90 nano, or whether Intel is planning to hedge their bet against a delayed Prescott introduction (due to power consumption/heat dissipation issues reported by OEM system developers)?
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BTW happy birthday sapasion
Bout the only quality post so far.Quote:
Originally posted by Moridin
This is a Xeon. It costs Intel nothing in R&D, and it's production cost is still well under 100$. Even if they only sell a few of them Intel stands to make a profit, so what reason could Intel have to not produce this chip?.
Heres a good read:
http://www.overclockers.com/articles830/
[sarcasm]Im am sure Intel is shaking frantically at the sight of athlon64 [/sarcasm]
?? Intel made a very VERY smart move here. I am sure they already have a profit analysis of the P4 EEs... Which probably wont be that bad, not gonna be great but it will still work. But thats not the goal here. The goal here is to $h17 on AMD's parade... If the P4 EE beats the Athlon64 in some benchies and the same for vice versa then things stay as they are. AMD doesnt get any more market shares and prices still stay high. As Moridin said this costs Intel a very small fraction of what AMD spent on the Opteron.... And IF the P4 EE performs on par with the top Athlon64 then they achieved their goal...
There is no delay in the relase of Prescott, and the power consumption was not reported by OEM system developers, but by Intel themselves.Quote:
Originally posted by JabberJaw
...whether Intel is planning to hedge their bet against a delayed Prescott introduction (due to power consumption/heat dissipation issues reported by OEM system developers)?
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BTW happy birthday sapasion
As well, this was not an issue so much as an un-expected result. The chip still conforms to intel specs, and is fit for distribution, it just might not be as good an overclocker as many here would have liked.
I believe this chip was released just so as to show some better numbers for benchmarks (not real world apps) where memory latency may be an issue in comparing it to the hammer with it's IMC.
will all this extra cache be worth the price tag???
Hard to say since they haven't released any pricing info yet. Could be $30 more or it could be 30% more, no one knows at this point.Quote:
Originally posted by richardginn
will all this extra cache be worth the price tag???
Hmmm.. 160M+ transistors... This is gonna be damn huge. Since the NW is ~55M and ~130mm^2 this is gonna be what? ~400mm^2?
Check your math, it would probably be closer to ~225mm^2Quote:
Originally posted by Chuck232
Hmmm.. 160M+ transistors... This is gonna be damn huge. Since the NW is ~55M and ~130mm^2 this is gonna be what? ~400mm^2?
I have sneaking suspicions that Intel may be using some hybrid technology to incorporate some of this cache (or all of the L3 cahce) at .09u for space savings.
macutty, in reply to some of your comments -
Quote "There is no delay in the relase of Prescott..."
See:
http://www.ocworkbench.com/ocwbcgi/n...63781566,6155,
http://www.aceshardware.com/forum?read=105038133
Quote "...and the power consumption was not reported by OEM system developers, but by Intel themselves."
http://www.theinquirer.net/?article=11588:
"There was another hotspot technology making the whisper rounds at IDF, it is called Prescott. Yeah, low blow, but a conversation with someone who would know told us that the numbers we hear about Prescott, 103w is on the low end of right, with 100-110w being enough to give SFF box engineers in Taiwan apoplectic fits. The power design spec of 88-103A at 1.35v is a lot of electrons flowing here and there."
(btw, I've read similar reports elsewhere. Rumors, granted, but such types of rumors have often been proven correct in the fullness of time.)
Quote "As well, this was not an issue so much as an un-expected result."
I used the word "issue" as the commonly-accepted euphemism for "problem", that is, an "unexpected result" that has a negative consequence (such as, for example, requiring a cooling fan that's louder than most customers will care to tolerate).
Anyway, it's fairly typical to run into tough problems while bringing technology products to market. None of this necessarily reflects badly on Intel, it's just part of the job.