Well, they could always limit it to one line. Offer an XP version with a 512K cache and 166MHz DDR FSB. This could become their new flagship, and could carry a nice little premium that could help them make some money.Quote:
Originally posted by Arcadian:
It's not about the hardware capability - like you say, it's practically already there. It's about the expense of supporting a number of new configurations that AMD would probably want to avoid. If Hammer is really less than a year away, why introduce a new line of products that will need support, when they can simply wait a little longer? Just my opinion.
Arcadian
The die manufacturing wouldn't change for a FSB change, it only affect the process at the level where the die is mounted to the OPGA.
I personally think AMD would be better off doing this vs. a 512K cache. The reason being, it you look at scaling, the Athlon does much better with FSB scaling. If you compare a Duron to the Athlon at the same FSB, there is not much difference except in programs where the data sets don't seem to fit into the Duron's substantially smaller 64K L2 cache. Right now, most data sets seem to fit OK into the 256K cache of the Athlon, P3, and P4 procs.
However, you are right in the perspective of it being harder to get full implementation of the platform for a bus increase. AMD would had to have notified the chipset vendors of their intentions, and given those manufacturers time to test and validate proper operation at that speed, plus the lead time to board makers to test and validate their designs and implementation. Adding another 256K of L2 cache would not require anything on the part of chipset or board makers.
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