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How come all of the "Mac People" still believe that their 500mhz G4s are faster than PC chips? What is the difference between them and pc chips like the PIII/IV and Athlon? Is it not a RISC processor, or am I wrong?
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they just need something to say that theyre better than us. The G4 can natively do more than a gigaflop, which is pretty good for a 500Mhz CPU (PC CPUs cant do that, but 1Ghz TBirds can). too bad mac just plain sucks and cant take advantage of that FPU
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Apple's IPC is considerably higher than its PC's counterpart. So instead of 500MHz, it would be much faster comparing to PIII 500MHz. However, that's the only good thing about it...personally I would never get a mac.
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Mac people are a bit psychotic, not to put to fine a point on things.
However, they principally believe that their RISC chips are much more elegant than x86 MPU's - and they are right. RISC architectures are inherently much simpler to design and understand (no (depending on the chip) decoders for instance).
They are far more economical on transistors (and therefore power) and the conventional wisdom is that something small and simple can be clocked higher. For example, think about birds (no not the really nice two legged ones that always turn me down http://dev.www.sharkyforums.forums.relay.cool/ , but the ones that fly). Humming birds can flap their wings at very high frequencies whereas condors have a slow beat.
OK, you are probably thinking this is wrong as the G4 is only clocked at 500MHz, but take a look at how quickly Intel got XScale to market at a clock rate of up to 1GHz (XScale is Intels latest StrongARM chip). I bet the XScale design team is vastly smaller than the P6 or Willamette design teams and the main reason is that it is a lot more simple to design a RISC processor.
I'm sure at this point someone is going to remind me of Alpha or USIII, so I'll just cover my back by adding that actually, in principle, it should be a lot simpler to design a RISC processor!
Anyway, thats the main reason that Mac people preach about their processors over x86 arch's and unfortunately, on this topic, I grudgingly agree with them.
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Peter Greenhalgh
'Argue with an idiot and he will drag you down to his level and beat you from experience.'
The problem with the G4 is that it is produced and developed by a company that was unable to clock it higher than 500Mhz for over 18 months. Motorola.
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I heard that the new G4+ are clocked higher only because they increased the pipeline.
Some tests showed that it didnt perform much better than the 500 of the original G4. Does that mean the branch prediction of G4s suck?
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I'm a salty veteran. Mmmmmmm...
IDRIS5 is correct, most of the Mac claims are based on the fact that the G4 is a RISC processor. The problem with this is modern X86 processors also operate as RISC processors after the instruction decode stage. The P4 actually caches its RISC like instructions generated by its decode stage (trace cache) thereby making it function entirely as a RISC processor most of the time.
The Other thing to consider is that RISC stands for Reduced Instruction Set Computing. The idea is that if you only a small number of simple instructions you can execute them faster and improve overall performance. This is a whole other debate though RISC clearly won out over CISC) The Problem with the G4 is that it acutely has one of the largest instruction sets around, even larger then the Athlon or PIII. (Itanium has a larger instruction set then the G4, but I think it may be the only processor that does)
(Yes this does mean that each RISC instruction does LESS then a typical CISC X86 instruction.)
Many of the FLOP claims are based on the G4's excellent SIMD unit. Using SIMD instructions the G4+ can in theory perform 8 32-bit floating-point operations per clock cycle. Mac fanatics like to then compare this number to what X86 processors can do with their standard X87 FPU. That is 1 per cycle for the PIII or P4. They also usually ignore the fact that the Athlon can theoretically perform 2 Floating point operations per cycle.
The Mac user then make the conclusion that the G4+ is 8 times as fast as an X86 processor of the same speed.
There are a couple problems with this. First the X87 FPU is a general-purpose IEEE compliant FPU and supports 32-bit 64-bit and 80-bit floating-point operations. The G4+ also has a general purpose IEEE compliant FPU (AFAIK it doesn’t support 80-bit operations though). The non-SIMD FPU of the G4 and G4+ has a peak of 1 FP op per cycle just like the PIII.
The second thing they tend to ignore is that X86 processors also have SIMD units (SSE, SSE2, and 3Dnow!). The SIMD units in the PIII, P4 and Athlon can theoretically perform 4 FP operations per cycle. Granted this is only half of what a G4+ can do (and the same as a regular G4). Even using SIMD a 1.7 GHz P4 has a higher theoretical instruction throughput then any G4+.
The third thing to remember, is that these are THERORETICAL numbers. Just being able to execute more instructions in a single clock cycle doesn’t mean that the program you are running has enough independent operations to actually do so. Furthermore your chances of keeping 4 SIMD slots fully occupied is much greater then the chances of keeping 8 units occupied. So running half the units at twice the speed will always yield better performance if all else is equal.
The other thing Mac users tend to ignore is memory. Even if you could find enough parallel instructions to keep 8 SIMD slots per cycle occupied it is very unlikely that the G4 has anywhere near enough memory bandwidth to keep this pace up. A PIII can often saturate its memory bandwidth using just its X86 unit executing just a single operation per clock. IIRC PC133 is quite new to the Mac and there is no DDR or RDRAM for it.
All that being said the G4 and G4+ have a number of more subtle advantages over the X86 chips. It has a shorter pipeline to reduce the cost of branch misprediction. More registers and 3-operand instructions make computations more efficient. It has a prefetch instruction that will load a block of memory into cache all at once to make the most efficient possible use of the FSB. It uses fewer transistors and generates less heat then X86 chips.
Overall, if an application is SIMD friendly and plays nice with cache the G4 can indeed keep up with top of the line X86 chips, but the number of applications where this is true is quite small. (A few PhotoShop filters and maybe some (SIMD optimized) RC5)
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The pipeline was extended to 7 stages form 4.Quote:
Originally posted by chickenlump2001:
I heard that the new G4+ are clocked higher only because they increased the pipeline.
Some tests showed that it didnt perform much better than the 500 of the original G4. Does that mean the branch prediction of G4s suck?
The G4 has not needed a great branch predictor on account of its short pipeline.
The other change in the G4 to the G4+ was that its SIMD capabilities were extended so it can now execute twice as many SIMD operations per cycle. (I.E. 8 32-bit operations as opposed to 4.)
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Life is complex. It has real and imaginary parts.
Alleged Steve Jobs quote, to Motorola reps, re. PowerPC:
"It'll be great in three years, when we're not using you any more"
PowerPC always promised huge performance, but after the 604e at 350MHz, things slowed down drastically. Now, the G4+ is languishing at half the clock speed of x86 CPUs: G4 may be faster per clock, but not twice as fast...(speaking as a Mac person who ain't fooled by the hype and wishes Apple would do something about the "speed" gap)
Stoo
[This message has been edited by stoo (edited June 19, 2001).]
I deleted this.
I'm not sure anymore and I can't find the reference anymore. https://www.sharkyforums.com/images/.../2005/06/5.gif
[This message has been edited by Moridin (edited June 19, 2001).]
I wish apple would go back to IBM
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I'm a salty veteran. Mmmmmmm...
Comparing clock speed on an x86 CPU (like a P3) and a PowerPC (like a G4) is not a very good way to compare the architectures or their real-word performace.
It takes many (from 5 - 20 average) micro-ops to perform one x86 instruction while the average G4 instruction takes only a few micro-ops. On both processors, each micro-op usually takes from 1-5 clock cycles. It is true that the RISC architecture does break down its instructions much moreso than an x86, but not enough to compensate for the difference.
As a result, a 500 Mhz G4 has approximately the same processing power as a 1 Ghz P3 in many cases (but not all). There are some cases (many games) where this difference is much less noticable because of the complex set of instructions required (which x86s are better designed for).
However, even with this fact, it is still true that x86 processors are approaching 2Ghz fast while PowerPCs are running at barely 800 Mhz. That, coupled with the fact that fewer programs are designed to run on a PowerPC based system makes the x86 architecture still worth considering.
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This is simply not true.Quote:
Originally posted by Racer^:
Comparing clock speed on an x86 CPU (like a P3) and a PowerPC (like a G4) is not a very good way to compare the architectures or their real-word performace.
It takes many (from 5 - 20 average) micro-ops to perform one x86 instruction while the average G4 instruction takes only a few micro-ops. On both processors, each micro-op usually takes from 1-5 clock cycles. It is true that the RISC architecture does break down its instructions much moreso than an x86, but not enough to compensate for the difference.
As a result, a 500 Mhz G4 has approximately the same processing power as a 1 Ghz P3 in many cases (but not all). There are some cases (many games) where this difference is much less noticable because of the complex set of instructions required (which x86s are better designed for).
First, The most common X86 operations translate into a single RISC operation. Overall in the PIII a single X86 operation translates on average to about 1.5 "RISC like" micro ops. Although the comparison is far from perfect, as a general rule you can consider a PIII micro op to be equivalent to a normal operation in a RISC processor.
Second modern processors are pipelined this means that the actual time it takes to complete an instruction (Instructions latency) is not that important. What counts is instruction throughput and the G4's throughput is limited to 2 RISC instructions per clock cycle, while the P6 can execute a maximum of 3 micro-ops per clock. (The Athlon can execute 3 load/store operations plus 3 integer/FP micro ops per clock) like I said the PIII tends to average about 1.5 micro ops per cycle so the G4 needs to be dammed efficient to even keep up with a PIII running the same clock speed.
In practice a G4 500 would outperform a (non cumine) PIII 500 by about 20% and an 500 MHz Athlon classic by 5-10%. Since then all these chips have added on die cache and PC133 (and the Athlon has DDR). Gives about the same benefit to each chip. The G4+ has had to lengthen its pipeline which likely decreases its performance by around 10% relative to a G4 of the same frequency.
This all adds up to the G4+ having about a 10% advantage over a PIII of the same speed, (733 MHz G4 is about the same as an 800 MHz cumine) and would likely perform a little below a 133 MHz FSB Athlon + DDR if you could find one running at that low of a frequency.
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Life is complex. It has real and imaginary parts.
I stand corrected.
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Can't we all just get along... Macs rule, if it weren't for the price I would totally get one.