DDR for Processors

OK, we all know how DDR works for memory... It uses both the rising edge and falling edge of the memory clock to read/write to memory? So basically the flip flops are rising edge and falling edge triggered. My question is, why don't they use this technology for the cpu clock? So a 1ghz cpu could perform like a 2ghz cpu. There must be a reason....

On a somewhat releated note, how do they manage to "quad-pump" the pentium4 fsb to 400mhz? I can see the "double-pump" by using the rising and falling edges, but not the quad-pump. Does it have to do with utilizing the dual channel memory interface on the 850, to sequentially access each channel? If so, how then can the 845 chipset also operate on a 400mhz bus? Or is the 845 only "double-pumped" to 200mhz?

A final question then, would be, would it be possible/advantageous to use a 4-way memory system by using 4 RDRAM channels instead of 2? There would still only be 64 traces for a 4x16 bit memory interface, which is the same as even an sdram system, so I don't imagine the cost would be too much over top of the 850. But it sure would provide a lot of bandwidth!

DDR is mostly useful as a signaling technology. It doesn’t mean things can happen any faster then they normally would. For example, there would not be any fundamental difference between CAS4 200 MHz SDRAM and CAS2 100 MHz DDR other then the way they reacted to the clock.

The advantage is signaling across the motherboard. With SDRAM the clock runs at twice the frequency of the data lines. It takes at least two full cycles for a data line to return to it’s original state. With DDR they run at the same frequency. This eases the signaling requirements on the motherboard. IIRC there is another important signaling advantage, I just can’t remember what it could be. :(

The P4’s quad data rate bus actual uses 2 100 MHz DDR strobes 90 deg out of phase, to achieve QDR. There are also some signaling technologies out there like Rambus’s QRSL that implement QDR by having 4 voltage levels rather then 2. This allows them to encode 2 bit in every transition of the data lines.

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Originally posted by Moridin


The advantage is signaling across the motherboard. With SDRAM the clock runs at twice the frequency of the data lines. It takes at least two full cycles for a data line to return to it’s original state. With DDR they run at the same frequency. This eases the signaling requirements on the motherboard. IIRC there is another important signaling advantage, I just can’t remember what it could be. :(

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I cannot understand what benewiths you are mentioning, as I know 100MHz DDR and 200MHz sdr signaling requires identical requirements for datalines as actual moving data is also identical. Where DDR helps is that needed triggering signal is only half the freguency of sdr, and that actual devices triggered are also working only half the actual freguency, is case with DDR-sdram there's memory chips that are triggered with rising edge and devices that are triggered with falling egde needing those memory chips installed in pairs, so actual memory chips are really close to sdr-sdram chips. With sdr-technology to have same througput you need to use twice higher memory freguency, or trigger that secondary memory chip with some extra technology like Kentron is doing with their memory technology, but having extra logic always costs some extra.

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Originally posted by naukkis


Where DDR helps is that needed triggering signal is only half the freguency of sdr, and that actual devices triggered are also working only half the actual freguency, is case with DDR-sdram there's memory chips that are triggered with rising edge and devices that are triggered with falling egde needing those memory chips installed in pairs, so actual memory chips are really close to sdr-sdram chips. With sdr-technology to have same througput you need to use twice higher memory freguency, or trigger that secondary memory chip with some extra technology like Kentron is doing with their memory technology, but having extra logic always costs some extra.

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I believe you are misinterpreting the internal structure of DDR. As far as I can tell it’s internal organization is no different from SDRAM, the only difference is the control logic.

To the internal device it matters very little whether it is being triggered on the rising edge 200 MHz or on the rising and falling edge at 100 MHz. In either case it is being strobed at 200 MHz, and has up to 5ns to complete it’s internal operation.

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Originally posted by Moridin


I believe you are misinterpreting the internal structure of DDR. As far as I can tell it’s internal organization is no different from SDRAM, the only difference is the control logic.

To the internal device it matters very little whether it is being triggered on the rising edge 200 MHz or on the rising and falling edge at 100 MHz. In either case it is being strobed at 200 MHz, and has up to 5ns to complete it’s internal operation.

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Hmmmm....

So what you're saying is the memory has only 5ns to complete its operation for 100mhz ddr (200mhz effective) as opposed to 100 mhz sdr which would have 10 ns to complete its operation? Then wouldn't this require much higher quality/faster ram chips than the sdram variant, resulting in a substantially higher cost? But my Radeon 7500, for instance, has its ddr memory rated at 4ns. But since it's running at 500mhz effectively, shouldn't it be rated for 2ns?

Thank-you.

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A final question then, would be, would it be possible/advantageous to use a 4-way memory system by using 4 RDRAM channels instead of 2? There would still only be 64 traces for a 4x16 bit memory interface, which is the same as even an sdram system, so I don't imagine the cost would be too much over top of the 850. But it sure would provide a lot of bandwidth!

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Sharp question. Actually, they are working on this . . . when the design process gets small enough it will be realized . . . have patience . . .

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IIRC there is another important signaling advantage, I just can’t remember what it could be.

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? I have to agree with naukkis here. Maybe the DDR specs have cleaner waves, but otherwise, I don't see any advantage. But hey, what do I know!

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Originally posted by Moridin


To the internal device it matters very little whether it is being triggered on the rising edge 200 MHz or on the rising and falling edge at 100 MHz. In either case it is being strobed at 200 MHz, and has up to 5ns to complete it’s internal operation.

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But that's not the case with DDR-sdram, it has two independent memory logigs which other is triggered with rising and other falling edge. For both memory chips situation is same like they were running the 100MHz:n clocks rising edges. Sure both logigs can be installed in one PGA-case but in internal it still has two independent memory areas which are triggered with different edges, and using different chips for rising and falling edge can be done, and that's what is the case with normal DDR-sdram Dimm. Wonder where that cas2 comes to DDR-sdram? That's the trigger count for the independent memory-logic. And using two interleaved low-speed memory logigs output looks just like there's just one output with twice the burst speed.

For DDR-II those independent triggered memory logigs are rised to four, probably putting every other edge to other memory cells. And rdram have used that 4-bit prefetch from the beginning but with no direct connection to memory bus.

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Originally posted by naukkis


But that's not the case with DDR-sdram, it has two independent memory logigs which other is triggered with rising and other falling edge. For both memory chips situation is same like they were running the 100MHz:n clocks rising edges. Sure both logigs can be installed in one PGA-case but in internal it still has two independent memory areas which are triggered with different edges, and using different chips for rising and falling edge can be done, and that's what is the case with normal DDR-sdram Dimm. Wonder where that cas2 comes to DDR-sdram? That's the trigger count for the independent memory-logic. And using two interleaved low-speed memory logigs output looks just like there's just one output with twice the burst speed.

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That is not what is described in Jedec’s publicly available documentation on DDR.

http://www.jedec.org/download/search/JESD79R1.pdf

Look at the functional diagrams starting on page 4. (8 pages in) There is clearly only one set of memory banks, not two.

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Originally posted by Moridin


That is not what is described in Jedec’s publicly available documentation on DDR.

http://www.jedec.org/download/search/JESD79R1.pdf

Look at the functional diagrams starting on page 4. (8 pages in) There is clearly only one set of memory banks, not two.

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That triggering method is not point in that Jedec presentation, but that page tells something about that 2n-prefetch what I tried to explain.

http://www.ecnmag.com/ecnmag/issues/...02/ec23ss1.asp

In DDR-sdram every memory block works half speed the actual memory throughput speed and every other memory cells are triggered to gave output with rising edge and every other with falling edge. Very easy way to double the actual memory throughput speed and keep other memory logic speed at reasonable level. Also impelementation to make old sdram-design to work in pairs to get double speed is easy as there's no need to modify the actual memory cells configuration.

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Originally posted by naukkis


That triggering method is not point in that Jedec presentation, but that page tells something about that 2n-prefetch what I tried to explain.

http://www.ecnmag.com/ecnmag/issues/...02/ec23ss1.asp

In DDR-sdram every memory block works half speed the actual memory throughput speed and every other memory cells are triggered to gave output with rising edge and every other with falling edge. Very easy way to double the actual memory throughput speed and keep other memory logic speed at reasonable level. Also impelementation to make old sdram-design to work in pairs to get double speed is easy as there's no need to modify the actual memory cells configuration.

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Ok, I see what you are getting at now, but that has more to do with the internal architecture and organization of the memory then the bus.

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It is important to understand all internal data transactions are made in pairs, and the transfer of write data from the input buffers to the internal memory array is made on sequential clock cycles (each positive clock edge). Therefore, if an odd number of data is written to the DDR SDRAM or if a write sequence is interrupted, the data mask signal must be used to prevent internal data corruption.

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It isn’t dependant on the DDR nature of the FSB, it’s just the mechanism used to achieve the desired data rate. You could just as readily implement this in a memory type with an SDR clock running at twice the internal speed. The reason why you would not do this is DDR has superior signalling properties, as I mentioned above.

This article also mentioned the other signalling advantage to the DDR spec (the one I couldn’t remember. DDR uses a differential clock.

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DDR also uses differential clocks (CK, CK#), and enables new data strobe (DQS) / data mask (DM) / clock enable (CKE) signals.

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This article also mentioned the other signalling advantage to the DDR spec (the one I couldn’t remember. DDR uses a differential clock.

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This is the one thing I thought you might be getting at, however I thought you meant that DDR signaling's physical characteristics were somehow superior to SDRAM. Differential signaling is possible with SDRAM.

One of the huge advantages of DDR over SDR is that the clock running across the motherboard traces is 1/2 the frequency. This makes the signal integrity engineering much simpler for the PCB layout people. As frequency ramps up, trace inductance and capacitance become significant issues, and it would be very ugly to have to terminate all those traces to impedence match them to the RAM/processor.

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Originally posted by Moridin


It isn’t dependant on the DDR nature of the FSB, it’s just the mechanism used to achieve the desired data rate. You could just as readily implement this in a memory type with an SDR clock running at twice the internal speed. The reason why you would not do this is DDR has superior signalling properties, as I mentioned above.

This article also mentioned the other signalling advantage to the DDR spec (the one I couldn’t remember. DDR uses a differential clock.

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Nope, for 200MHz:n sdram chips core logic needs to be able to handle 200MHz:n clock, or would I say 200 hundred million operations per second, for 100MHz DDR-sdram the chips core's halves just need to do that 100MHz or 100 million operations per second. That differential signaling for clocking is actually not only needed for signaling purposes but both falling and rising edge sensing logigs can be same with differential signaling.

That memory chips working methods can be seen eg. in integrated solutions, 166MHz DDR-sdram is much cheaper than 200MHz sdram as actual logic working freguencies are key for production expenses.

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Originally posted by naukkis


Nope, for 200MHz:n sdram chips core logic needs to be able to handle 200MHz:n clock, or would I say 200 hundred million operations per second, for 100MHz DDR-sdram the chips core's halves just need to do that 100MHz or 100 million operations per second. That differential signaling for clocking is actually not only needed for signaling purposes but both falling and rising edge sensing logigs can be same with differential signaling.

That memory chips working methods can be seen eg. in integrated solutions, 166MHz DDR-sdram is much cheaper than 200MHz sdram as actual logic working freguencies are key for production expenses.

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But that is only because the standard for SDRAM says it must be so. When developing a new standard there is no fundamental reason other then the signaling advantages of a DDR scheme that it had to be done that way.

Jedec could have developed a standard that had a 200 MHz single data rate clock instead using the exact same internal structure. There is no fundamental link between the two concepts other then the fact Jedec chose to use both in their DDR SDRAM standard. The internal structure they chose to achieve the desired data rate is in no way connected to DDR in general.

One thing I'm curious about naukkis: if you don't think RAM latencies are that important, then why is the EV7 built with 8 small channels of RDRAM and not one or two large channels of RDRAM? The way the EV7 bus is designed gives me the impression that they tried to keep the latencies to a minimum.

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Originally posted by elimc
One thing I'm curious about naukkis: if you don't think RAM latencies are that important, then why is the EV7 built with 8 small channels of RDRAM and not one or two large channels of RDRAM? The way the EV7 bus is designed gives me the impression that they tried to keep the latencies to a minimum.

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Maybe it's for granularity (being favourable to latency also), just as GeForce3/4 have 4 independant memory-controllers working together to have the same advantage

you can either acces multiple smaller datachunks separated over the controllers, or use them together to acces one big datachunk, depending on what you need

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Originally posted by elimc
One thing I'm curious about naukkis: if you don't think RAM latencies are that important, then why is the EV7 built with 8 small channels of RDRAM and not one or two large channels of RDRAM? The way the EV7 bus is designed gives me the impression that they tried to keep the latencies to a minimum.

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Memory latencies eat bandwith, eg memory subsystem without latencies achieve it's theoretical bandwith, the more the latencies the more achievable bandwith suffer compared to theoretical. So latencies do matter, but you have very tiny performance advantage with same bandwith and reduced latency.

But EV7 is not like it is because that, rdram-chips are designed working independently and if you want to use one or two large channel everything needs to be redesigned. DDR-sdram have to use packed with large channels because it's have very poor and ineffective design with it's command bus, but if it's possible, like with point to point devices eg. Nvidia cards they also implement independent memory channels not for reduced latency but for more memory bandwith coming from taller memory bursts which decreases overall memory latencies.

It’s also possible that the EV7 doesn’t need the bandwidth provided by 8 RDRAM channels, and it is designed that way for other reasons. One possibility that comes to mind is the designers used 8 channels in order to efficiently support very large memory configurations rather then any particular need for that much bandwidth.

I don't have anything more to say than: Thanks guys.