I understand basic electrical theory. DDR (Double Data Read) is as I understand it transmitting data on both halves of a sine wave. One clock cycle is one sine wave with a positive half upward and a negative half downward. What I do not understand is how Intel gets 4 transmissions of data, ie, 800 mhz out of one clock cycle. Is this all a marketing ploy or am I missing something in very basic electrical theory????