Itanium - any comments?

[Arcadian]

Yes, it's me, Arcadian, and everybody is starting to realize now, that servers are my favorite kinds of computers. That's why I want to open the floor to comments about Intel's new IA-64 architecture, and their upcoming Itanium chip.

What do you guys think of Itanium? Are there any major worries or drawbacks that you foresee? Do you think it will be successful, in spite of being late? What do you think of Intel pushing an instruction set that is completely new? Anyone out there with confidence in Itanium? Does anyone out there not know what Itanium is?

We can discuss anything here, including what people think of AMD's Sledgehammer, and if it will compete with the Itanium processor. I happen to be the kind of person who has a lot of confidence in Itanium, but I would love a discussion that can proove me wrong. If anyone has any technical specifications they can list, or ideas of what may be included in the architecture, please speak up! This should be an interesting conversation.

[Humus]

Well, I think the Itanium is hot ... well, literally, with it 320 million transistors ...
But actually, I feel like Itanium will not be a hit, while I do believe in the IA-64 archetecture. What will be the main disadvantage of the Itanium is lack of applications. This will probably change by the time, but it took like 10 years to move over to 32bit ...

About the Sledgehammer, well, I was kinda disappointed when I heard of it first. I hoped that they would follow the IA-64 route, but they probably realized the 64bit need a little to late. They just didn't have to time to do a completely new design.

[Down8]

I really want an Itanium. Or, rather, any IA-64 processor. if the P4 doesn't kill Intel, I would probably go with that over the Sledgehammer [but when I next upgrade it will be to a T'bird].

It will take some years to completely tranfer over to 64bit, but Win9x still had compatible code to make use of 16bit stuff, so I expect that Whistler will be similar for 32bit.

-bZj

------------------
.sig: coming soon to a post near you!

[jtshaw]

Intel has a lot of power over companies out there. I know HP and Intel worked hard getting lots of linux stuff ported to IA-64 (now basically anything that runs on linux runs on IA-64..though it was supposively very easy to do). MS apparently has a windows os that will run IA-64 now too. With some pressure from MS and Intel people will fold and start ported there software over to IA-64. It won't happen overnight but it will probably happen sooner then many may think. You have to take in account that most software packages don't need to be ported to IA-64 because when it first comes around it will be for expensive servers only. This will give non-server software designers plenty of time to port there stuff if IA-64 is to ever become mainstream. Anyway, I think the major stepping stone will be Intel actually getting the Itanium out there....if I am not mistaken it is almost pushing a whole year late....

------------------
My computer said "WindowsME/2000 or better" so I installed Linux.

[jaywallen]

What do I think of the "Itanium"? I hope that the marketing guys who think of the names for these things should be dope-slapped. I'm gettin' tired of made-up names on cars, CPUs and children. Maybe they should call this thing the "Unobtainium"!

:P

Regards,
Jim

Actually, I'm looking forward to the chip and the architecture on which it stands.

[Arcadian]

jtshaw, I have heard that there are already over 400 apps compiled in native IA-64 already. This includes a lot of scientific apps as well.

One professor from a University (I forget which one) runs scientific programs and said that there was a routine that he used to run on the supercomputers of two years ago that took a day to complete and get data. On a 4 processor Itanium system (he has one of the Pilot release systems), this same task took less than 1/2 hour. Granted that computers have matured over the last two years, but to get a 48x improvement over a supercomputer seemed impressive to me!

I think there will be a lot of software apps available for Itanium by launch (I think I read somewhere that launch was in Q1 2001). I also think Itanium will give Ultrasparc III a run for its money.

Also, this comment is for jaywallen. What parts of the architecture do you forward to the most?

[jtshaw]

I certainly don't doubt that, I know basically everything running on Linux or BSD runs on IA-64. I don't know much about what has been ported Windows wise but I know the OS has and I would assume anything developed for servers or by universities would be the first to go over. I think the Itanium will be a mid to high end server wrecking ball when Intel gets them out the door. UltraSparc III is going to get a run for the money I believe.

Originally posted by Arcadian:
jtshaw, I have heard that there are already over 400 apps compiled in native IA-64 already. This includes a lot of scientific apps as well.

One professor from a University (I forget which one) runs scientific programs and said that there was a routine that he used to run on the supercomputers of two years ago that took a day to complete and get data. On a 4 processor Itanium system (he has one of the Pilot release systems), this same task took less than 1/2 hour. Granted that computers have matured over the last two years, but to get a 48x improvement over a supercomputer seemed impressive to me!

I think there will be a lot of software apps available for Itanium by launch (I think I read somewhere that launch was in Q1 2001). I also think Itanium will give Ultrasparc III a run for its money.

Also, this comment is for jaywallen. What parts of the architecture do you forward to the most?

------------------
My computer said "WindowsME/2000 or better" so I installed Linux.

[Moridin]

My biggest concern about Itanium is the high transistor count and large power requirements. While these are not really a problem themselves they may be indicative of underlying problems, in particular they indicate a very complex design.

I would not normally worry about a complex design but Itanium EPIC architecture is based on VLIW, and the primary goal of VLIW is to simplify the chip design. This is accomplished by using the compiler to find parallelism rather then dedicated hardware built into the chip.

I wonder why the chip is so complex. IMHO EPIC should have resulted in simple, small, fast chip, not a large complex, slow (in MHz) chip. The other concern is, now that you have shifted complexity into the compiler from hardware it makes the compiler much more difficult to write.

The rise if RISC architectures in the late 80's and early 90's came in large part from the recognition that careful selection of the ISA could simplify both the compiler and the micro-architecture of the processor. This resulted in better implementation of both and yielded better performance then CISC processors, even though the CISC processors had more powerful instruction sets.

Since then Intel has done an amazing job at keeping up and even passing most RISC architectures. The cost was that both chips and compilers were larger and harder to design then for a RISC chip of equivalent power.

It remains to be seen whether the complexity of Itanium is the result of this being the first IA-64 processor, or if it indicates Intel made some fundamental mistakes when it defined the IA-64 ISA.

[Moridin]

A few more points.

I like the idea of allowing the compiler to do a lot of the work of finding parallelism, but I don't think this allows you to completely eliminate OOOE which is what Intel has tried with Itanium. OOOE allows you deal with some problems that VLIW/EPIC cannot handle on its own.

You do not know at compile time if your data is in cache or main memory. You can prefetch and hope it is there by the time you need it, but this will not always work, and if it fails the processor may sit idle for hundreds of cycles. OOOE on the other hand can deal with the problem dynamically when it occures.

The second problem associated with the lack of OOOE is that OOOE resources are the same as the resources required by SMT. I can't see IA-64 doing SMT without adding OOOE as well. This would add complexity and defeat the VLIW/EPIC concept of eliminating complexity by eliminating OOOE.

In the long run though the combination of explicit parallelism with an out of order core could be very powerful, if the IA-64 ISA can be made to do OOOE.

The other problem I have is the support for IA-32. I'd be willing to bet that a lot of the complexity of Itanium comes from IA-32 support. Intel would have been much better of not supporting it.

[Moridin]

Originally posted by Humus:
Well, I think the Itanium is hot ... well, literally, with it 320 million transistors ...
But actually, I feel like Itanium will not be a hit, while I do believe in the IA-64 archetecture. What will be the main disadvantage of the Itanium is lack of applications. This will probably change by the time, but it took like 10 years to move over to 32bit ...

About the Sledgehammer, well, I was kinda disappointed when I heard of it first. I hoped that they would follow the IA-64 route, but they probably realized the 64bit need a little to late. They just didn't have to time to do a completely new design.

IA-64 will be a server/workstation chip for quite some time and may never move down into the desktop. As such it doesn’t need all that much in the way of software support. As long as Oracle, SGI's graphic app (what is it called again? MAYA?) and a few other key apps are ported IA-64 will be ok in this regard.

As far as OS support goes I'm sure HP will port HP-UX. That along with Dynamo will give IA-64 access to almost all current server and workstation applications.

[Moridin]

Ok, I'll try for four posts in a row.

I just wanted to add that in the high-end server market a powerful processor is not an absolute requirement. Sun's USII processors have performed well below most of its competitors over the last 5 years yet Sun has been very successful in that time. At the same time the Alpha, which is the fastest processor available has done poorly.

In this market the apps lend themselves to multiple processors so the power of the individual processors is less important then the multi-processor implementation. I.E. the bus, memory system, chipset and OS. If you do these things well you can actually increase you sales since the customer buys more processors to do the same job and the fastest system is the one with the most processors.

[JabberJaw]

Sorry, what's EPIC? VLIW? OOOE? Thanks

[Arcadian]

Originally posted by Moridin:
My biggest concern about Itanium is the high transistor count and large power requirements. While these are not really a problem themselves they may be indicative of underlying problems, in particular they indicate a very complex design.

As long as Itanium can be air cooled, it doesn't matter how large it is, or how high the power requirements go. In the high end server world, it's trivial to get more fans and larger power supplies.

In fact, I'm sure the general mood during design was to get high performance, even if you have to brute force it. In other words, if there is a method of getting 5% performance, but it increases the core temperature a few degrees, do it anyways.

From what I understand about McKinley, a smaller die size, and lower power were more of a factor in design. McKinley was also designed fairly independantly from Merced (Itanium), so there were many differences in implementations. The biggest difference was that Merced had to come out first, so a small die with lower power was less of an issue.

Originally posted by Moridin:
I would not normally worry about a complex design but Itanium EPIC architecture is based on VLIW, and the primary goal of VLIW is to simplify the chip design. This is accomplished by using the compiler to find parallelism rather then dedicated hardware built into the chip.

This is true for VLIW, but not for EPIC. VLIW is very compiler intensive, while EPIC is a mix between compiler and hardware assisted optimizations.

Originally posted by Moridin:
I wonder why the chip is so complex. IMHO EPIC should have resulted in simple, small, fast chip, not a large complex, slow (in MHz) chip. The other concern is, now that you have shifted complexity into the compiler from hardware it makes the compiler much more difficult to write.

Again, complexity came from trying to get the chip to debut quicker. McKinley will have a much smaller core, AFAIK.

It's also true that the compiler is tougher to write, but as I said above, there is hardware that continues to optimize the code.

Originally posted by Moridin:
The rise if RISC architectures in the late 80's and early 90's came in large part from the recognition that careful selection of the ISA could simplify both the compiler and the micro-architecture of the processor. This resulted in better implementation of both and yielded better performance then CISC processors, even though the CISC processors had more powerful instruction sets.

Since then Intel has done an amazing job at keeping up and even passing most RISC architectures. The cost was that both chips and compilers were larger and harder to design then for a RISC chip of equivalent power.

Good point, and excellent observation. A chips performance can often times be in the implementation rather than the architecture.

Originally posted by Moridin:
It remains to be seen whether the complexity of Itanium is the result of this being the first IA-64 processor, or if it indicates Intel made some fundamental mistakes when it defined the IA-64 ISA.

The IA-64 ISA began its design in the early '90s. It was created by some of the brightest minds in the industry. Chances are that the IA-64 ISA is pretty sound. The complexity of the die itself is not likely going to affect performance, in my opinion. Sure an optimized layout would be preferable, and we'll likely see that with McKinley.

[Arcadian]

Originally posted by JabberJaw:
Sorry, what's EPIC? VLIW? OOOE? Thanks

VLIW = Very Long Instruction Word. It is an Instruction Set Architecture (ISA), just like RISC and CISC are ISAs, but the difference is that the compiler can take a bundle of instructions, and align them so that they are more "friendly" for the processor. This way, there are certain optimizations that can be done to the CPU that can really improve performance. However, it does assume that you have a perfect compiler, and those are hard to make . Transmetta's Crusoe chip is a VLIW processor.

EPIC = Explicitly Parellel Instruction-set Computer. This is an ISA based on VLIW, but it takes it to another level of practicality. Instead of depending 100% on the compiler, the processor also has hardware to optimize code. This gives the best of both worlds of VLIW and CISC. IA-64 is the first EPIC ISA, and we will have to see if it was worth it.

OOOE = Out Of Order Execution. In the old days, instructions were fed to processors In Order. This is ok, but sometimes the processor has to wait for data to load from memory. An Out Of Order computer can execute other instructions while waiting for the first one to receive data. The P6 and K7 architectures both use OOOE, but VIA's Cyrix III does not. The Itanium is In Order, but the theory is that the compiler will order the instructions in a better way than an Out Of Order engine. Fortunately for EPIC, if the compiler does not, the CPU can still optimize further (this is limited, however). I'm eagerly waiting to see how the Itanium does.

Hope this answers you questions .

[Bash]

Concerning Itanium complexity...

I guess that from what I've heard the Itanium shouldn't be an excessively complex chip. This is primarily due to its EPIC architecture -- because the instruction scheduling is done in the compiler, the Itanium doesn't need to include the excessively complicated instruction scheduling circuitry. I can't remember the number any more, but I think the P3 instruction scheduler takes a sizeable percentage of the chip area.

So the question of the day is where do the all the transistors in the Itanium get used. One candidate is the register file. I believe the Itanium has 128 usable registers. What's that, about 10x the number of registers available in the x86 architecture? Also, I've heard the first generation Itanium mantains backward compatability with x86 binaries by having some kind of instruction translation hardware built in -- this must take a bit of space too. I suppose if they have any free transistors after that we can just pray for more functional units


-Bash