Hammer presentation up...

[Conrad Song]

At the AMD website. Unfortunately, the slides are notably ambiguous. Thumbs down for me.

[Snare]

The only interesting information I picked up from the slideshow was that apparently the Hammer will have an integrated memory controller & northbridge. Will adding that functionality to the CPU result in relatively expensive CPUs and cheap motherboards?

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The Balance of a Gaming System:
1. A CPU capable of getting you at least 70FPS in the games you play.
2. A motherboard that's rock stable.
3. RAM with the lowest latency possible & enough that your system does not have to use a HDD swapfile.
4. A graphics card that can get you at least 70FPS in the highest resolution that you play.
5. A fast HDD for level loading (7200RPM or faster).
6. A nice big display to show the power of your rig

[Conrad Song]

Originally posted by Snare:
The only interesting information I picked up from the slideshow was that apparently the Hammer will have an integrated memory controller & northbridge. Will adding that functionality to the CPU result in relatively expensive CPUs and cheap motherboards?

I'm sure that gets "factored" in. However, I wouldn't expect motherboard prices to drop, someone still has to make money. The integrated memory controller is there purely for performance.

Where the cost may come in is the HyperTransport I/O. While this will provide a huge boost in I/O bandwidth (especially since it is separate from the memory controller), there needs to be adapters to convert between HyperTransport and the standard in question (AGP/PCI/...). Furthermore, HyperTransport is high-speed serial, which can be expensive to test. From the looks of it, there are 3 HyperTransport links on die.

[Moridin]

Originally posted by Snare:
The only interesting information I picked up from the slideshow was that apparently the Hammer will have an integrated memory controller & northbridge. Will adding that functionality to the CPU result in relatively expensive CPUs and cheap motherboards?

It depends, the integrated memory controller can simplify the chipset a lot and that should save some money, but it also increases the number of pins on the processor. If the number of pins on the processor goes to high the cost for manufacturing the motherboard start to go up dramatically.



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Life is complex. It has real and imaginary parts.

[Marsolin]

Originally posted by Moridin:
It depends, the integrated memory controller can simplify the chipset a lot and that should save some money, but it also increases the number of pins on the processor. If the number of pins on the processor goes to high the cost for manufacturing the motherboard start to go up dramatically.

Number of pins on the processor is one of the things I want to see. For the 128-bit DDR interface we are talking about >200 pins for a chipset, and I can't think of why it would be less here. Hypertransport will also take up quite a few since there are three links. I didn't see the widths specified though.

Speaking if HyperTransport, maybe someone can explain something to me. I've been getting confused by mix ups of "B" and "b" and where they use the term pairs.

One presentation I got from http://www.hypertransport.org stated that an interface with 16-bits each direction has a total bandwidth of 6.4GB/s. What? That should be 32 bits total at 800MHz, which is 3.2GB/s to my math. Is there some level of detail I am missing here?

It also seems that this interface has 64 data bits total, and that would explain the bandwidth, but not the notation. I read the description as 16 differential pairs in each direction, which means that the silent half of the pair shouldn't be included in BW calculations.

As for the unstated width of the Hammer Hypertransport links I can only figure it based upon the aggregate BW given for an 8-way system of 25GB/s. That means 6.4GB/s per link. That would seem to indicate a 16-bit per direction interface based upon the specs (if not my math). The specs also claim that as 76 high speed pins; ~103 if you include others. Multiply that times three interfaces and we are talking about >300 pins. Add DDR and we are over 500 (more likely >600). And that doesn't even include the normal power and grounds needed for the processor.

And does anyone else see memory bandwidth limitations for Clawhammer here? Although great latency. 2.7GB/s max in a UP system seems pretty limited in that timeframe. Especially since it can't be easily improved since it is integrated. Does anyone know what the Hammer follow-on plans are for DDR-II?


[This message has been edited by Marsolin (edited October 17, 2001).]